intel: fix the gen 11 compute shader scratch IDs

Scratch space allocation is based on the number of threads in the base
configuration, and we only have one base configuration for ICL, with 8
subslices.

This fixes an issue with Aztec on Vulkan in a machine with a
configuration that's not the base. The issue looks like a regression
from b9e93db20896, but it seems things are broken since forever, just
not easily reproducible.

v2: Reimplement it using the subslices variable. Don't touch TGL.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>

diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c
index 01b08f24b9303a0ebb5b869a09363836c2398ea7..701cfa20aea4362fd217b19ee5687ee113f2e9e8 100644 (file)
--- a/src/gallium/drivers/iris/iris_program.c
+++ b/src/gallium/drivers/iris/iris_program.c
@@ -2053,9 +2053,14 @@ iris_get_scratch_space(struct iris_context *ice,
     * as well.  This is not currently documented at all.
     *
     * This hack is no longer necessary on Gen11+.
+    *
+    * For, ICL, scratch space allocation is based on the number of threads
+    * in the base configuration.
     */
    unsigned subslice_total = screen->subslice_total;
-   if (devinfo->gen < 11)
+   if (devinfo->gen == 11)
+      subslice_total = 8;
+   else if (devinfo->gen < 11)
       subslice_total = 4 * devinfo->num_slices;
    assert(subslice_total >= screen->subslice_total);
 

diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 7965008e06092990c34ae517ba60338950475d99..112a12014cb846740ff723c74b808f364fbd154f 100644 (file)
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -1395,7 +1395,12 @@ anv_scratch_pool_alloc(struct anv_device *device, struct anv_scratch_pool *pool,
 
    const struct gen_device_info *devinfo = &device->info;
 
-   const unsigned subslices = MAX2(device->physical->subslice_total, 1);
+   unsigned subslices = MAX2(device->physical->subslice_total, 1);
+
+   /* For, ICL, scratch space allocation is based on the number of threads
+    * in the base configuration. */
+   if (devinfo->gen == 11)
+      subslices = 8;
 
    unsigned scratch_ids_per_subslice;
    if (devinfo->gen >= 11) {

diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 4a76ee58ddde8b838d871c83d12ebd76e6f2008c..9933eb27e7e1f6c4473caf19db966f59886de010 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -467,8 +467,13 @@ brw_alloc_stage_scratch(struct brw_context *brw,
        * brw->screen->subslice_total is the TOTAL number of subslices
        * and we wish to view that there are 4 subslices per slice
        * instead of the actual number of subslices per slice.
+       *
+       * For, ICL, scratch space allocation is based on the number of threads
+       * in the base configuration.
        */
-      if (devinfo->gen >= 9 && devinfo->gen < 11)
+      if (devinfo->gen == 11)
+         subslices = 8;
+      else if (devinfo->gen >= 9 && devinfo->gen < 11)
          subslices = 4 * brw->screen->devinfo.num_slices;
 
       unsigned scratch_ids_per_subslice;