stats: updates due to changes to x86, stale configs.

author Nilay Vaish <nilay@cs.wisc.edu>

Sat, 11 Oct 2014 21:18:51 +0000 (16:18 -0500)

committer Nilay Vaish <nilay@cs.wisc.edu>

Sat, 11 Oct 2014 21:18:51 +0000 (16:18 -0500)
author Nilay Vaish <nilay@cs.wisc.edu>
Sat, 11 Oct 2014 21:18:51 +0000 (16:18 -0500)
committer Nilay Vaish <nilay@cs.wisc.edu>
Sat, 11 Oct 2014 21:18:51 +0000 (16:18 -0500)
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini

index 8f8a452cd58ed0ef33ced5d88f809bbbb2ce9f8c..20e3fa665f61b9b3557aac688feba54806100dec 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
@@ -648,10 +648,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -730,7 +731,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -776,11 +777,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -808,8 +810,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -818,6 +845,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -831,19 +859,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -932,6 +967,7 @@ HeaderType=0
  InterruptLine=30
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1387,6 +1423,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini

index 646b919837925433fe43a335ec57ca161c6e1d88..f8b77d3d8a912d267155dcd1097115b33187668f 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -90,6 +90,7 @@ do_statistics_insts=true
  dtb=system.cpu0.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -142,7 +143,6 @@ switched_out=false
  system=system
  tracer=system.cpu0.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  dcache_port=system.cpu0.dcache.cpu_side
@@ -596,6 +596,7 @@ do_statistics_insts=true
  dtb=system.cpu1.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -648,7 +649,6 @@ switched_out=false
  system=system
  tracer=system.cpu1.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  dcache_port=system.cpu1.dcache.cpu_side
@@ -1139,7 +1139,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -1220,11 +1220,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -1252,8 +1253,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -1262,6 +1288,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -1275,19 +1302,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -1315,10 +1349,11 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -1387,6 +1422,7 @@ HeaderType=0
  InterruptLine=30
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1842,6 +1878,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini

index 7628c37720dc339b75ace255b6acc53f4fb79e72..30c3fd76c69f95d0329ac632852ff7aa59f244eb 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -90,6 +90,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -142,7 +143,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  dcache_port=system.cpu.dcache.cpu_side
@@ -597,10 +597,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -679,7 +680,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -725,11 +726,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -757,8 +759,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -767,6 +794,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -780,19 +808,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -881,6 +916,7 @@ HeaderType=0
  InterruptLine=30
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1336,6 +1372,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini

index d6b54e8750259fe75c531a50e5f3402349a9bc23..7ff9bd5337ca946197306d15eb86f08a20486730 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
@@ -84,9 +84,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -273,6 +270,7 @@ do_statistics_insts=true
  dtb=system.cpu2.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -325,7 +323,6 @@ switched_out=true
  system=system
  tracer=system.cpu2.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  
@@ -740,7 +737,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -821,11 +818,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -853,8 +851,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -863,6 +886,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -876,19 +900,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -916,10 +947,11 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -988,6 +1020,7 @@ HeaderType=0
  InterruptLine=30
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1443,6 +1476,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini

index b768d26a92caf061ab8e69de101c1ed2554234a5..a0c959df8e886111d7d14f8af5e1d9ee67ecf483 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
@@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain
  
  [system.cpu0]
  type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer
+children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
  branchPred=system.cpu0.branchPred
  checker=Null
  clk_domain=system.cpu_clk_domain
@@ -184,14 +184,14 @@ predType=tournament
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
@@ -199,15 +199,15 @@ sequential_access=false
  size=32768
  system=system
  tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu0.toL2Bus.slave[1]
  
  [system.cpu0.dcache.tags]
  type=LRU
-assoc=4
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
@@ -237,7 +237,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[5]
+port=system.cpu0.toL2Bus.slave[5]
  
  [system.cpu0.dtb]
  type=ArmTLB
@@ -254,7 +254,7 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu0.toL2Bus.slave[3]
  
  [system.cpu0.executeFuncUnits]
  type=MinorFUPool
@@ -643,34 +643,34 @@ opClass=InstPrefetch
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
  size=32768
  system=system
  tags=system.cpu0.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu0.toL2Bus.slave[0]
  
  [system.cpu0.icache.tags]
  type=LRU
-assoc=1
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
  size=32768
  
@@ -729,7 +729,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[4]
+port=system.cpu0.toL2Bus.slave[4]
  
  [system.cpu0.itb]
  type=ArmTLB
@@ -746,7 +746,71 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
  
  [system.cpu0.tracer]
  type=ExeTracer
@@ -754,7 +818,7 @@ eventq_index=0
  
  [system.cpu1]
  type=MinorCPU
-children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer
+children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
  branchPred=system.cpu1.branchPred
  checker=Null
  clk_domain=system.cpu_clk_domain
@@ -839,14 +903,14 @@ predType=tournament
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
@@ -854,15 +918,15 @@ sequential_access=false
  size=32768
  system=system
  tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[7]
+mem_side=system.cpu1.toL2Bus.slave[1]
  
  [system.cpu1.dcache.tags]
  type=LRU
-assoc=4
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
@@ -892,7 +956,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[11]
+port=system.cpu1.toL2Bus.slave[5]
  
  [system.cpu1.dtb]
  type=ArmTLB
@@ -909,7 +973,7 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[9]
+port=system.cpu1.toL2Bus.slave[3]
  
  [system.cpu1.executeFuncUnits]
  type=MinorFUPool
@@ -1298,34 +1362,34 @@ opClass=InstPrefetch
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
  size=32768
  system=system
  tags=system.cpu1.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[6]
+mem_side=system.cpu1.toL2Bus.slave[0]
  
  [system.cpu1.icache.tags]
  type=LRU
-assoc=1
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
  size=32768
  
@@ -1384,7 +1448,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[10]
+port=system.cpu1.toL2Bus.slave[4]
  
  [system.cpu1.itb]
  type=ArmTLB
@@ -1401,7 +1465,71 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[8]
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
  
  [system.cpu1.tracer]
  type=ExeTracer
@@ -1429,13 +1557,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -1460,7 +1588,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -1509,11 +1637,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -1541,8 +1670,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -1551,6 +1705,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -1564,19 +1719,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -1584,12 +1746,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -1644,6 +1806,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1728,6 +1891,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
@@ -2046,15 +2219,16 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
  master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
  
  [system.vncserver]
  type=VncServer
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini

index dcd779005c9beec18ffb4dbc6d750d577af2c623..240d456d31909104158afcd50db34f3db14c3132 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
@@ -784,10 +784,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -820,13 +821,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -851,7 +852,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -865,11 +866,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -897,8 +899,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -907,6 +934,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -920,19 +948,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -940,12 +975,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -1000,6 +1035,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1084,6 +1120,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini

index 26a641846f76ed616f3b7f4ed32adcf31ee53e3f..a708031a081cb4bdbbfd659a2a305d5052ba9875 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -37,7 +37,7 @@ load_offset=0
  machine_type=RealView_PBX
  mem_mode=timing
  mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
  multi_proc=true
  num_work_ids=16
  panic_on_oops=true
@@ -101,10 +101,10 @@ voltage_domain=system.voltage_domain
  type=DerivO3CPU
  children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -119,19 +119,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu.fuPool
  function_trace=false
@@ -151,20 +152,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -182,7 +183,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  dcache_port=system.cpu.dcache.cpu_side
@@ -190,8 +190,8 @@ icache_port=system.cpu.icache.cpu_side
  
  [system.cpu.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -203,7 +203,7 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu.checker]
  type=O3Checker
@@ -433,14 +433,14 @@ port=system.cpu.toL2Bus.slave[3]
  
  [system.cpu.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
  eventq_index=0
  
  [system.cpu.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu.fuPool.FUList0.opList
  
@@ -453,10 +453,10 @@ opLat=1
  
  [system.cpu.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
  
  [system.cpu.fuPool.FUList1.opList0]
  type=OpDesc
@@ -468,275 +468,233 @@ opLat=3
  [system.cpu.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
  
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
  
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
  
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
+opLat=9
  
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu.icache]
  type=BaseCache
@@ -883,10 +841,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -919,13 +878,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -950,7 +909,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -964,11 +923,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -996,8 +956,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -1006,6 +991,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -1019,19 +1005,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -1039,12 +1032,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -1099,6 +1092,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1183,6 +1177,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini

index 319208ed0fe6107a7d3ab44f1f51e39f4883bd5a..a054d64a714d4e2eda524b8101dc4a1b1951cb5c 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -99,12 +99,12 @@ voltage_domain=system.voltage_domain
  
  [system.cpu0]
  type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
+children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -119,19 +119,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu0.dstage2_mmu
  dtb=system.cpu0.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu0.fuPool
  function_trace=false
@@ -151,20 +152,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -182,7 +183,6 @@ switched_out=false
  system=system
  tracer=system.cpu0.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  dcache_port=system.cpu0.dcache.cpu_side
@@ -190,8 +190,8 @@ icache_port=system.cpu0.icache.cpu_side
  
  [system.cpu0.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -203,20 +203,20 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu0.dcache]
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
@@ -224,15 +224,15 @@ sequential_access=false
  size=32768
  system=system
  tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu0.toL2Bus.slave[1]
  
  [system.cpu0.dcache.tags]
  type=LRU
-assoc=4
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
@@ -262,7 +262,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[5]
+port=system.cpu0.toL2Bus.slave[5]
  
  [system.cpu0.dtb]
  type=ArmTLB
@@ -279,18 +279,18 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu0.toL2Bus.slave[3]
  
  [system.cpu0.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4
  eventq_index=0
  
  [system.cpu0.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu0.fuPool.FUList0.opList
  
@@ -303,10 +303,10 @@ opLat=1
  
  [system.cpu0.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
+opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2
  
  [system.cpu0.fuPool.FUList1.opList0]
  type=OpDesc
@@ -318,308 +318,266 @@ opLat=3
  [system.cpu0.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu0.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu0.fuPool.FUList2.opList0]
+[system.cpu0.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu0.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu0.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu0.fuPool.FUList2.opList
  
-[system.cpu0.fuPool.FUList2.opList2]
+[system.cpu0.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu0.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
-
-[system.cpu0.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu0.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu0.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu0.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu0.fuPool.FUList4.opList
+opList=system.cpu0.fuPool.FUList3.opList
  
-[system.cpu0.fuPool.FUList4.opList]
+[system.cpu0.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu0.fuPool.FUList5]
+[system.cpu0.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
+opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25
  
-[system.cpu0.fuPool.FUList5.opList00]
+[system.cpu0.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu0.fuPool.FUList5.opList01]
+[system.cpu0.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu0.fuPool.FUList5.opList02]
+[system.cpu0.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu0.fuPool.FUList5.opList03]
+[system.cpu0.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu0.fuPool.FUList5.opList04]
+[system.cpu0.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu0.fuPool.FUList5.opList05]
+[system.cpu0.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu0.fuPool.FUList5.opList06]
+[system.cpu0.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu0.fuPool.FUList5.opList07]
+[system.cpu0.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu0.fuPool.FUList5.opList08]
+[system.cpu0.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu0.fuPool.FUList5.opList09]
+[system.cpu0.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu0.fuPool.FUList5.opList10]
+[system.cpu0.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu0.fuPool.FUList5.opList11]
+[system.cpu0.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu0.fuPool.FUList5.opList12]
+[system.cpu0.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu0.fuPool.FUList5.opList13]
+[system.cpu0.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu0.fuPool.FUList5.opList14]
+[system.cpu0.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu0.fuPool.FUList5.opList15]
+[system.cpu0.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu0.fuPool.FUList5.opList16]
+[system.cpu0.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu0.fuPool.FUList5.opList17]
+[system.cpu0.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu0.fuPool.FUList5.opList18]
+[system.cpu0.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu0.fuPool.FUList5.opList19]
+[system.cpu0.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
+opLat=9
  
-[system.cpu0.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu0.fuPool.FUList6.opList
-
-[system.cpu0.fuPool.FUList6.opList]
+[system.cpu0.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu0.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu0.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu0.fuPool.FUList7.opList0]
+[system.cpu0.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu0.fuPool.FUList7.opList1]
+[system.cpu0.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu0.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu0.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu0.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu0.fuPool.FUList8.opList]
+[system.cpu0.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu0.icache]
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
  size=32768
  system=system
  tags=system.cpu0.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu0.toL2Bus.slave[0]
  
  [system.cpu0.icache.tags]
  type=LRU
-assoc=1
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
  size=32768
  
@@ -678,7 +636,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[4]
+port=system.cpu0.toL2Bus.slave[4]
  
  [system.cpu0.itb]
  type=ArmTLB
@@ -695,7 +653,71 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
  
  [system.cpu0.tracer]
  type=ExeTracer
@@ -703,12 +725,12 @@ eventq_index=0
  
  [system.cpu1]
  type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
+children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -723,19 +745,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=1
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu1.dstage2_mmu
  dtb=system.cpu1.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu1.fuPool
  function_trace=false
@@ -755,20 +778,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -786,7 +809,6 @@ switched_out=false
  system=system
  tracer=system.cpu1.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  dcache_port=system.cpu1.dcache.cpu_side
@@ -794,8 +816,8 @@ icache_port=system.cpu1.icache.cpu_side
  
  [system.cpu1.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -807,20 +829,20 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu1.dcache]
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
@@ -828,15 +850,15 @@ sequential_access=false
  size=32768
  system=system
  tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[7]
+mem_side=system.cpu1.toL2Bus.slave[1]
  
  [system.cpu1.dcache.tags]
  type=LRU
-assoc=4
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
@@ -866,7 +888,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[11]
+port=system.cpu1.toL2Bus.slave[5]
  
  [system.cpu1.dtb]
  type=ArmTLB
@@ -883,18 +905,18 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[9]
+port=system.cpu1.toL2Bus.slave[3]
  
  [system.cpu1.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4
  eventq_index=0
  
  [system.cpu1.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu1.fuPool.FUList0.opList
  
@@ -907,10 +929,10 @@ opLat=1
  
  [system.cpu1.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
+opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2
  
  [system.cpu1.fuPool.FUList1.opList0]
  type=OpDesc
@@ -922,308 +944,266 @@ opLat=3
  [system.cpu1.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu1.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu1.fuPool.FUList2.opList0]
+[system.cpu1.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu1.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu1.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu1.fuPool.FUList2.opList
  
-[system.cpu1.fuPool.FUList2.opList2]
+[system.cpu1.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu1.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
-
-[system.cpu1.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu1.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu1.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu1.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu1.fuPool.FUList4.opList
+opList=system.cpu1.fuPool.FUList3.opList
  
-[system.cpu1.fuPool.FUList4.opList]
+[system.cpu1.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu1.fuPool.FUList5]
+[system.cpu1.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
+opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25
  
-[system.cpu1.fuPool.FUList5.opList00]
+[system.cpu1.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu1.fuPool.FUList5.opList01]
+[system.cpu1.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu1.fuPool.FUList5.opList02]
+[system.cpu1.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu1.fuPool.FUList5.opList03]
+[system.cpu1.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu1.fuPool.FUList5.opList04]
+[system.cpu1.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu1.fuPool.FUList5.opList05]
+[system.cpu1.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu1.fuPool.FUList5.opList06]
+[system.cpu1.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu1.fuPool.FUList5.opList07]
+[system.cpu1.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu1.fuPool.FUList5.opList08]
+[system.cpu1.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu1.fuPool.FUList5.opList09]
+[system.cpu1.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu1.fuPool.FUList5.opList10]
+[system.cpu1.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu1.fuPool.FUList5.opList11]
+[system.cpu1.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu1.fuPool.FUList5.opList12]
+[system.cpu1.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu1.fuPool.FUList5.opList13]
+[system.cpu1.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu1.fuPool.FUList5.opList14]
+[system.cpu1.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu1.fuPool.FUList5.opList15]
+[system.cpu1.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu1.fuPool.FUList5.opList16]
+[system.cpu1.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu1.fuPool.FUList5.opList17]
+[system.cpu1.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu1.fuPool.FUList5.opList18]
+[system.cpu1.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu1.fuPool.FUList5.opList19]
+[system.cpu1.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
-
-[system.cpu1.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu1.fuPool.FUList6.opList
+opLat=9
  
-[system.cpu1.fuPool.FUList6.opList]
+[system.cpu1.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu1.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu1.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu1.fuPool.FUList7.opList0]
+[system.cpu1.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu1.fuPool.FUList7.opList1]
+[system.cpu1.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu1.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu1.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu1.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu1.fuPool.FUList8.opList]
+[system.cpu1.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu1.icache]
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
  size=32768
  system=system
  tags=system.cpu1.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[6]
+mem_side=system.cpu1.toL2Bus.slave[0]
  
  [system.cpu1.icache.tags]
  type=LRU
-assoc=1
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
  size=32768
  
@@ -1282,7 +1262,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[10]
+port=system.cpu1.toL2Bus.slave[4]
  
  [system.cpu1.itb]
  type=ArmTLB
@@ -1299,7 +1279,71 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[8]
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
  
  [system.cpu1.tracer]
  type=ExeTracer
@@ -1327,13 +1371,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -1358,7 +1402,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -1407,11 +1451,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -1439,8 +1484,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -1449,6 +1519,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -1462,19 +1533,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -1482,12 +1560,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -1542,6 +1620,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1626,6 +1705,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
@@ -1944,15 +2033,16 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
  master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
  
  [system.vncserver]
  type=VncServer
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

index 240be98a7a614db55c440296f65d17d1d0f91348..51ab195cc05a8a4e5b3564678197f520115a44f7 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -101,10 +101,10 @@ voltage_domain=system.voltage_domain
  type=DerivO3CPU
  children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -119,19 +119,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu.fuPool
  function_trace=false
@@ -151,20 +152,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -182,7 +183,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  dcache_port=system.cpu.dcache.cpu_side
@@ -190,8 +190,8 @@ icache_port=system.cpu.icache.cpu_side
  
  [system.cpu.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -203,7 +203,7 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu.dcache]
  type=BaseCache
@@ -283,14 +283,14 @@ port=system.cpu.toL2Bus.slave[3]
  
  [system.cpu.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
  eventq_index=0
  
  [system.cpu.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu.fuPool.FUList0.opList
  
@@ -303,10 +303,10 @@ opLat=1
  
  [system.cpu.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
  
  [system.cpu.fuPool.FUList1.opList0]
  type=OpDesc
@@ -318,275 +318,233 @@ opLat=3
  [system.cpu.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
  
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
  
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
  
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
+opLat=9
  
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu.icache]
  type=BaseCache
@@ -733,10 +691,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -769,13 +728,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -800,7 +759,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -814,11 +773,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -846,8 +806,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -856,6 +841,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -869,19 +855,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -889,12 +882,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -949,6 +942,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1033,6 +1027,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr

index 9dee17aa29828dc69864b0007a25e0e853b600aa..056f4dd22ef35b527e52c92f61ecdd865778c27a 100755 (executable)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
@@ -1,6 +1,7 @@
  warn: Sockets disabled, not accepting vnc client connections
  warn: Sockets disabled, not accepting terminal connections
  warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
  warn: The clidr register always reports 0 caches.
  warn: clidr LoUIS field of 0b001 to match current ARM implementations.
  warn: The csselr register isn't implemented.
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini

index 0158d21869b8da92bfa08791f4500516e57c9b29..8a89971a1bfab53c05a9997addc01d514f1eb89a 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
@@ -37,7 +37,7 @@ load_offset=0
  machine_type=RealView_PBX
  mem_mode=atomic
  mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
  multi_proc=true
  num_work_ids=16
  panic_on_oops=true
@@ -124,9 +124,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -504,6 +501,7 @@ dstage2_mmu=system.cpu2.dstage2_mmu
  dtb=system.cpu2.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -527,7 +525,7 @@ max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
  numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
  numPhysFloatRegs=256
  numPhysIntRegs=256
  numROBEntries=192
@@ -557,7 +555,6 @@ switched_out=true
  system=system
  tracer=system.cpu2.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  
@@ -1018,13 +1015,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -1049,7 +1046,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -1098,11 +1095,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -1130,8 +1128,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -1140,6 +1163,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -1153,19 +1177,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -1173,12 +1204,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -1233,6 +1264,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1317,6 +1349,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
@@ -1635,10 +1677,11 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini

index 0248bee209cb663a375d03a067e1507facb7246b..5d2c59c2af7c8dca8a9177c4f739afe92acd31e9 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
@@ -129,6 +129,7 @@ dstage2_mmu=system.cpu0.dstage2_mmu
  dtb=system.cpu0.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -152,7 +153,7 @@ max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
  numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
  numPhysFloatRegs=256
  numPhysIntRegs=256
  numROBEntries=192
@@ -182,7 +183,6 @@ switched_out=false
  system=system
  tracer=system.cpu0.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  dcache_port=system.cpu0.dcache.cpu_side
@@ -733,6 +733,7 @@ dstage2_mmu=system.cpu1.dstage2_mmu
  dtb=system.cpu1.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -756,7 +757,7 @@ max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
  numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
  numPhysFloatRegs=256
  numPhysIntRegs=256
  numROBEntries=192
@@ -786,7 +787,6 @@ switched_out=true
  system=system
  tracer=system.cpu1.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  
@@ -1247,13 +1247,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -1278,7 +1278,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -1327,11 +1327,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -1359,8 +1360,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -1369,6 +1395,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -1382,19 +1409,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -1402,12 +1436,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -1462,6 +1496,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1546,6 +1581,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
@@ -1864,10 +1909,11 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini

index bc1aaf76da7c53b98ccb0219a3af77ae5dc32f5b..8b812b09c7cefe91fda5a3f904fe93d314c88e0e 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
@@ -37,7 +37,7 @@ load_offset=0
  machine_type=RealView_PBX
  mem_mode=timing
  mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
  multi_proc=true
  num_work_ids=16
  panic_on_oops=true
@@ -487,13 +487,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -518,7 +518,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -567,11 +567,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -599,8 +600,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -609,6 +635,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -622,19 +649,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -642,12 +676,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -702,6 +736,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -786,6 +821,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
@@ -1104,10 +1149,11 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini

index beeca581e9a788aa821115fb42a54259d69c1d74..68a408e3f444651c1260308330636b2da24e002c 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -75,7 +75,7 @@ type=Bridge
  clk_domain=system.clk_domain
  delay=50000
  eventq_index=0
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
  req_size=16
  resp_size=16
  master=system.iobus.slave[0]
@@ -120,6 +120,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -172,7 +173,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  dcache_port=system.cpu.dcache.cpu_side
@@ -730,10 +730,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -762,8 +763,8 @@ transition_latency=100000000
  
  [system.e820_table]
  type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
  eventq_index=0
  
  [system.e820_table.entries0]
@@ -789,6 +790,13 @@ size=133169152
  
  [system.e820_table.entries3]
  type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
  addr=4294901760
  eventq_index=0
  range_type=2
@@ -837,13 +845,13 @@ version=17
  [system.intel_mp_table.base_entries02]
  type=X86IntelMPBus
  bus_id=0
-bus_type=ISA
+bus_type=PCI
  eventq_index=0
  
  [system.intel_mp_table.base_entries03]
  type=X86IntelMPBus
  bus_id=1
-bus_type=PCI
+bus_type=ISA
  eventq_index=0
  
  [system.intel_mp_table.base_entries04]
@@ -853,7 +861,7 @@ dest_io_apic_intin=16
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
  source_bus_irq=16
  trigger=ConformTrigger
  
@@ -864,7 +872,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=0
  trigger=ConformTrigger
  
@@ -875,7 +883,7 @@ dest_io_apic_intin=2
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=0
  trigger=ConformTrigger
  
@@ -886,7 +894,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=1
  trigger=ConformTrigger
  
@@ -897,7 +905,7 @@ dest_io_apic_intin=1
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=1
  trigger=ConformTrigger
  
@@ -908,7 +916,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=3
  trigger=ConformTrigger
  
@@ -919,7 +927,7 @@ dest_io_apic_intin=3
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=3
  trigger=ConformTrigger
  
@@ -930,7 +938,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=4
  trigger=ConformTrigger
  
@@ -941,7 +949,7 @@ dest_io_apic_intin=4
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=4
  trigger=ConformTrigger
  
@@ -952,7 +960,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=5
  trigger=ConformTrigger
  
@@ -963,7 +971,7 @@ dest_io_apic_intin=5
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=5
  trigger=ConformTrigger
  
@@ -974,7 +982,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=6
  trigger=ConformTrigger
  
@@ -985,7 +993,7 @@ dest_io_apic_intin=6
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=6
  trigger=ConformTrigger
  
@@ -996,7 +1004,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=7
  trigger=ConformTrigger
  
@@ -1007,7 +1015,7 @@ dest_io_apic_intin=7
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=7
  trigger=ConformTrigger
  
@@ -1018,7 +1026,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=8
  trigger=ConformTrigger
  
@@ -1029,7 +1037,7 @@ dest_io_apic_intin=8
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=8
  trigger=ConformTrigger
  
@@ -1040,7 +1048,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=9
  trigger=ConformTrigger
  
@@ -1051,7 +1059,7 @@ dest_io_apic_intin=9
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=9
  trigger=ConformTrigger
  
@@ -1062,7 +1070,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=10
  trigger=ConformTrigger
  
@@ -1073,7 +1081,7 @@ dest_io_apic_intin=10
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=10
  trigger=ConformTrigger
  
@@ -1084,7 +1092,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=11
  trigger=ConformTrigger
  
@@ -1095,7 +1103,7 @@ dest_io_apic_intin=11
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=11
  trigger=ConformTrigger
  
@@ -1106,7 +1114,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=12
  trigger=ConformTrigger
  
@@ -1117,7 +1125,7 @@ dest_io_apic_intin=12
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=12
  trigger=ConformTrigger
  
@@ -1128,7 +1136,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=13
  trigger=ConformTrigger
  
@@ -1139,7 +1147,7 @@ dest_io_apic_intin=13
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=13
  trigger=ConformTrigger
  
@@ -1150,7 +1158,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=14
  trigger=ConformTrigger
  
@@ -1161,15 +1169,15 @@ dest_io_apic_intin=14
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=14
  trigger=ConformTrigger
  
  [system.intel_mp_table.ext_entries]
  type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
  eventq_index=0
-parent_bus=1
+parent_bus=0
  subtractive_decode=true
  
  [system.intrctrl]
@@ -1178,7 +1186,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -1224,11 +1232,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -1473,6 +1482,7 @@ HeaderType=0
  InterruptLine=14
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=9223372036854775808
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1763,8 +1773,33 @@ pio=system.iobus.master[9]
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -1773,6 +1808,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -1786,19 +1822,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

index 02f62080c1aa5b8559b4294e87a6a3249833e718..9ab6b9d663a2e482e51b30251445940800c7cb0d 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,125 +1,125 @@
  
  ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.129877                       # Number of seconds simulated
-sim_ticks                                5129876981500                       # Number of ticks simulated
-final_tick                               5129876981500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.125902                       # Number of seconds simulated
+sim_ticks                                5125902116500                       # Number of ticks simulated
+final_tick                               5125902116500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
  sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 181923                       # Simulator instruction rate (inst/s)
-host_op_rate                                   359604                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2288414721                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 752624                       # Number of bytes of host memory used
-host_seconds                                  2241.67                       # Real time elapsed on the host
-sim_insts                                   407812863                       # Number of instructions simulated
-sim_ops                                     806114915                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 125787                       # Simulator instruction rate (inst/s)
+host_op_rate                                   248644                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1580293827                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 793336                       # Number of bytes of host memory used
+host_seconds                                  3243.64                       # Real time elapsed on the host
+sim_insts                                   408006726                       # Number of instructions simulated
+sim_ops                                     806511598                       # Number of ops (including micro ops) simulated
  system.voltage_domain.voltage                       1                       # Voltage in Volts
  system.clk_domain.clock                          1000                       # Clock period in ticks
  system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         4096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1048192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10832768                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11913792                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1048192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1048192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6597248                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker         4800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1043840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10813760                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11891200                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1043840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1043840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6604544                       # Number of bytes written to this memory
  system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9587328                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9594624                       # Number of bytes written to this memory
  system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           64                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16378                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             169262                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                186153                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          103082                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           75                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16310                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             168965                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                185800                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          103196                       # Number of write requests responded to by this memory
  system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               149802                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide         5527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            798                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               204331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2111701                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2322432                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          204331                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             204331                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1286044                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       582876                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1868920                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1286044                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       588402                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           798                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              204331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2111701                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4191352                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        186153                       # Number of read requests accepted
-system.physmem.writeReqs                       149802                       # Number of write requests accepted
-system.physmem.readBursts                      186153                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     149802                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11895360                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18432                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9586112                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11913792                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9587328                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      288                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total               149916                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         5531                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            936                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             87                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               203640                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2109631                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2319826                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          203640                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             203640                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1288465                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       583328                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1871792                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1288465                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       588859                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           936                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            87                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              203640                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2109631                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4191618                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        185800                       # Number of read requests accepted
+system.physmem.writeReqs                       149916                       # Number of write requests accepted
+system.physmem.readBursts                      185800                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     149916                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11876224                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     14976                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9592960                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11891200                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9594624                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      234                       # Number of DRAM read bursts serviced by the write queue
  system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1739                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11465                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11004                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11873                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11540                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11961                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11322                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11640                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11420                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11351                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11861                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11826                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              12031                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11538                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12375                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11569                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11089                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10234                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9627                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9640                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9149                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9237                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9047                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8744                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8727                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9070                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9221                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9815                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9405                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9499                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9604                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9640                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9124                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           1736                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11489                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10946                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11982                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11463                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11671                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11298                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11252                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11687                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11071                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11217                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11355                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              12125                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11861                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12651                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12184                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11314                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9710                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9082                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8978                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8996                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9462                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9601                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9097                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8837                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                9327                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9159                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9532                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9463                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9618                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9862                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9881                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9285                       # Per bank write bursts
  system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5129876930000                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5125902065000                       # Total gap between requests
  system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  186153                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  185800                       # Read request sizes (log2)
  system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 149802                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    171145                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     11892                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2095                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       399                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        51                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 149916                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    170703                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     12067                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2038                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       421                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        56                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
@@ -159,115 +159,115 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
  system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
  system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
  system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     8641                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     8986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     9732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    10392                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    11488                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9974                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7930                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7619                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2237                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7637                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7787                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     8527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     8842                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     9565                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    10246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    11384                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    10610                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9929                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7958                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7723                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7617                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       46                       # What write queue length does an incoming req see
  system.physmem.wrQLenPdf::53                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        72700                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      295.480165                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     175.038242                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     318.841917                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          28215     38.81%     38.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17447     24.00%     62.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7490     10.30%     73.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4112      5.66%     78.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3047      4.19%     82.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2009      2.76%     85.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1387      1.91%     87.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1145      1.57%     89.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7848     10.80%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          72700                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7372                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.211883                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      559.387781                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7371     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::54                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       11                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        72846                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      294.719271                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.256286                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     318.919065                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          28471     39.08%     39.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17446     23.95%     63.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7310     10.03%     73.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4243      5.82%     78.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2987      4.10%     82.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1984      2.72%     85.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1403      1.93%     87.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1126      1.55%     89.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7876     10.81%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          72846                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7377                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.152094                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      560.212559                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7376     99.99%     99.99% # Reads before turning the bus around for writes
  system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7372                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7372                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.317824                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.630780                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.249046                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6322     85.76%     85.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              58      0.79%     86.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              24      0.33%     86.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             276      3.74%     90.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             291      3.95%     94.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              18      0.24%     94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              12      0.16%     94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              14      0.19%     95.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              37      0.50%     95.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               4      0.05%     95.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.04%     95.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               3      0.04%     95.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             249      3.38%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.04%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.05%     99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               4      0.05%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              19      0.26%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               7      0.09%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.03%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             6      0.08%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             7      0.09%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            7377                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7377                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.318558                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.615023                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.539295                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6330     85.81%     85.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              64      0.87%     86.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              33      0.45%     87.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             268      3.63%     90.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             287      3.89%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              24      0.33%     94.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              24      0.33%     95.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              16      0.22%     95.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              20      0.27%     95.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               2      0.03%     95.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.08%     95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.03%     95.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             237      3.21%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.04%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               2      0.03%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               3      0.04%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              11      0.15%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.01%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              12      0.16%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             3      0.04%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             6      0.08%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             3      0.04%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.18%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.01%     99.99% # Writes before turning the bus around for reads
  system.physmem.wrPerTurnAround::144-147             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7372                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2030519500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5515488250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    929325000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10924.70                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total            7377                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2068154250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5547516750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    927830000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11145.11                       # Average queueing delay per DRAM burst
  system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29674.70                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29895.11                       # Average memory access latency per DRAM burst
  system.physmem.avgRdBW                           2.32                       # Average DRAM read bandwidth in MiByte/s
  system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MiByte/s
  system.physmem.avgRdBWSys                        2.32                       # Average system read bandwidth in MiByte/s
@@ -276,146 +276,146 @@ system.physmem.peakBW                        12800.00                       # Th
  system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
  system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
  system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.49                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.68                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     152396                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    110551                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.99                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15269535.89                       # Average gap between requests
-system.physmem.pageHitRate                      78.34                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4923406969000                       # Time in different power states
-system.physmem.memoryStateTime::REF      171297620000                       # Time in different power states
+system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.36                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     151753                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    110856                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.78                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.95                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15268566.48                       # Average gap between requests
+system.physmem.pageHitRate                      78.28                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4919748958000                       # Time in different power states
+system.physmem.memoryStateTime::REF      171165020000                       # Time in different power states
  system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       35172289500                       # Time in different power states
+system.physmem.memoryStateTime::ACT       34988035500                       # Time in different power states
  system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 267480360                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 282131640                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 145946625                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 153940875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                719347200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                730392000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               482144400                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               488449440                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          335058144720                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          335058144720                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          129492550125                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          129753331110                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          2964331954500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          2964103199250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            3430497567930                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            3430569589035                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.729942                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.743982                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              662528                       # Transaction distribution
-system.membus.trans_dist::ReadResp             662520                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13776                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13776                       # Transaction distribution
-system.membus.trans_dist::Writeback            103082                       # Transaction distribution
+system.physmem.actEnergy::0                 267185520                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 283530240                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 145785750                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 154704000                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                715946400                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                731460600                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               477984240                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               493302960                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          334798779120                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          334798779120                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          129305495790                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          129519356940                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          2962113436500                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          2961925839000                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            3427824613320                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            3427906972860                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.726542                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.742609                       # Core power per rank (mW)
+system.membus.trans_dist::ReadReq              662592                       # Transaction distribution
+system.membus.trans_dist::ReadResp             662582                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13889                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13889                       # Transaction distribution
+system.membus.trans_dist::Writeback            103196                       # Transaction distribution
  system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
  system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2203                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1739                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133413                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133410                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1645                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1645                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3290                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3290                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471084                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775070                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       478447                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1724617                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94802                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        94802                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1822709                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6580                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241828                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550137                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18482688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20274653                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq             2215                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1736                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133104                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133101                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1644                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1644                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           10                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471544                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775066                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       477864                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           20                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1724494                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94793                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        94793                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1822575                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       242058                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550129                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18467392                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20259579                       # Cumulative packet size per connected master and slave (bytes)
  system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3018432                       # Cumulative packet size per connected master and slave (bytes)
  system.membus.pkt_size_system.iocache.mem_side::total      3018432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                23299665                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              943                       # Total snoops (count)
-system.membus.snoop_fanout::samples            338647                       # Request fanout histogram
+system.membus.pkt_size::total                23284587                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              949                       # Total snoops (count)
+system.membus.snoop_fanout::samples            338415                       # Request fanout histogram
  system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
  system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
  system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
  system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  338647    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  338415    100.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
  system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              338647                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           251233500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              338415                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           251687000                       # Layer occupancy (ticks)
  system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           583254000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           583226500                       # Layer occupancy (ticks)
  system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3290000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3288000                       # Layer occupancy (ticks)
  system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1574333248                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1575195000                       # Layer occupancy (ticks)
  system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                9500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy               13500                       # Layer occupancy (ticks)
  system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1645000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1644000                       # Layer occupancy (ticks)
  system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         3160566012                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         3157657266                       # Layer occupancy (ticks)
  system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           55015741                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           54931743                       # Layer occupancy (ticks)
  system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47584                       # number of replacements
-system.iocache.tags.tagsinuse                0.103867                       # Cycle average of tags in use
+system.iocache.tags.replacements                47575                       # number of replacements
+system.iocache.tags.tagsinuse                0.091458                       # Cycle average of tags in use
  system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47600                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47591                       # Sample count of references to valid blocks.
  system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4992945897000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.103867                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006492                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.006492                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4992976867000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.091458                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005716                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005716                       # Average percentage of cache occupancy
  system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
  system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
  system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428751                       # Number of tag accesses
-system.iocache.tags.data_accesses              428751                       # Number of data accesses
+system.iocache.tags.tag_accesses               428670                       # Number of tag accesses
+system.iocache.tags.data_accesses              428670                       # Number of data accesses
  system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
  system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide          919                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              919                       # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          919                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               919                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          919                       # number of overall misses
-system.iocache.overall_misses::total              919                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    156299196                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    156299196                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    156299196                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    156299196                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    156299196                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    156299196                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          919                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            919                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_misses::pc.south_bridge.ide          910                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              910                       # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          910                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               910                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          910                       # number of overall misses
+system.iocache.overall_misses::total              910                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    152161446                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    152161446                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    152161446                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    152161446                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    152161446                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    152161446                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          910                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            910                       # number of ReadReq accesses(hits+misses)
  system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
  system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          919                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             919                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          919                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            919                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          910                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             910                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          910                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            910                       # number of overall (read+write) accesses
  system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
  system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
  system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
  system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
  system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
  system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170075.294886                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 170075.294886                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170075.294886                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 170075.294886                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170075.294886                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 170075.294886                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 167210.380220                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 167210.380220                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 167210.380220                       # average overall miss latency
  system.iocache.blocked_cycles::no_mshrs           308                       # number of cycles access was blocked
  system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.iocache.blocked::no_mshrs                   26                       # number of cycles access was blocked
@@ -424,22 +424,22 @@ system.iocache.avg_blocked_cycles::no_mshrs    11.846154                       #
  system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.iocache.fast_writes                      46720                       # number of fast writes performed
  system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          919                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          919                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          910                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
  system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
  system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          919                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          919                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          919                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          919                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    108481196                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    108481196                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   2843906419                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2843906419                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    108481196                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    108481196                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    108481196                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    108481196                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          910                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          910                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          910                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          910                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104814946                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    104814946                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   2846577667                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2846577667                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    104814946                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    104814946                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    104814946                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    104814946                       # number of overall MSHR miss cycles
  system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
  system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
  system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
@@ -448,14 +448,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
  system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
  system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
  system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 118042.650707                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60871.284653                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60871.284653                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 118042.650707                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 118042.650707                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60928.460338                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60928.460338                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 115181.259341                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 115181.259341                       # average overall mshr miss latency
  system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
  system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
  system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -469,12 +469,12 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
  system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
  system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
  system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq               225575                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              225575                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57606                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57606                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1645                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1645                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               225681                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              225681                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57721                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57721                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1644                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1644                       # Transaction distribution
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
@@ -487,18 +487,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27236                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27696                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       471084                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95278                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95278                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3290                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3290                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  569652                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       471544                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95260                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95260                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3288                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3288                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  570092                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
@@ -511,19 +511,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13618                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13848                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       241828                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027896                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027896                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6580                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3276304                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3920684                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total       242058                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027824                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027824                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3276458                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3917656                       # Layer occupancy (ticks)
  system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
  system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
  system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -549,7 +549,7 @@ system.iobus.reqLayer11.occupancy              170000                       # La
  system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
  system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            20374000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            20719000                       # Layer occupancy (ticks)
  system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
  system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
@@ -559,273 +559,273 @@ system.iobus.reqLayer16.occupancy                9000                       # La
  system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
  system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           422027356                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           422009356                       # Layer occupancy (ticks)
  system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
  system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           460198000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           460543000                       # Layer occupancy (ticks)
  system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            52381259                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            52362257                       # Layer occupancy (ticks)
  system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1645000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1644000                       # Layer occupancy (ticks)
  system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
  system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                86898883                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86898883                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            901790                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             80120336                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                78166165                       # Number of BTB hits
+system.cpu.branchPred.lookups                86911006                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          86911006                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            901724                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             80066722                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                78189070                       # Number of BTB hits
  system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.560955                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1553548                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             177807                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.654891                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1556278                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             178526                       # Number of incorrect RAS predictions.
  system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        449490093                       # number of cpu cycles simulated
+system.cpu.numCycles                        449563158                       # number of cpu cycles simulated
  system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
  system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27736713                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      428990683                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86898883                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79719713                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     417726391                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1890728                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     147536                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                50079                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        202600                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       127031                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          405                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9184683                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                447260                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5357                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          446936119                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.894164                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.051823                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27553144                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      429142218                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86911006                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79745348                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     417985667                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1891240                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     143316                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                50930                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        210883                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       127962                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          502                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9183903                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                446388                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4881                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          447018024                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.894555                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.051977                       # Number of instructions fetched each cycle (Total)
  system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                281459283     62.98%     62.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2262059      0.51%     63.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72137620     16.14%     79.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1613997      0.36%     79.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2155091      0.48%     80.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2322801      0.52%     80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1535694      0.34%     81.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1854025      0.41%     81.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81595549     18.26%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                281457902     62.96%     62.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2285728      0.51%     63.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72178245     16.15%     79.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1597297      0.36%     79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2150673      0.48%     80.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2329203      0.52%     80.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1531441      0.34%     81.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1871505      0.42%     81.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81616030     18.26%    100.00% # Number of instructions fetched each cycle (Total)
  system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
  system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
  system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            446936119                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.193328                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.954394                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 23065529                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             264763767                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 150736142                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7425317                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 945364                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              838360092                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 945364                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25914691                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               223241691                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       13213057                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 154633432                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              28987884                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              834905613                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                478581                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12335118                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 182483                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               13727584                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           997265714                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1813395255                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1114768158                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               110                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             964051126                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 33214586                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             466449                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         470370                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  38986770                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17343174                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10196687                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1348761                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1124760                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  829365293                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1208199                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 824078412                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            244412                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23515910                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     36291432                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         152927                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     446936119                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.843839                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.418170                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            447018024                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.193323                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.954576                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 22975502                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             264891753                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 150781344                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7423805                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 945620                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              838588132                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 945620                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25820685                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               223318475                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       13301995                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 154670533                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              28960716                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              835102889                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                477440                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12397064                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 181319                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               13705397                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           997542850                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1813799496                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1115056771                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               257                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             964533940                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 33008908                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             469072                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         473209                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  39003947                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17327061                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10187947                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1305152                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1075480                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  829577981                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1211612                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 824337261                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            238496                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        23343623                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     36066463                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         155823                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     447018024                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.844081                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.418172                       # Number of insts issued each cycle
  system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           262716607     58.78%     58.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13881580      3.11%     61.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            10086185      2.26%     64.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6914821      1.55%     65.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            74322504     16.63%     82.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4455510      1.00%     83.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72776226     16.28%     99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1206411      0.27%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              576275      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           262761301     58.78%     58.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            13855312      3.10%     61.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10080748      2.26%     64.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6920312      1.55%     65.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            74355494     16.63%     82.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4460813      1.00%     83.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72820654     16.29%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1197568      0.27%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              565822      0.13%    100.00% # Number of insts issued each cycle
  system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
  system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
  system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       446936119                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       447018024                       # Number of insts issued each cycle
  system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1975200     71.80%     71.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                    252      0.01%     71.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                    1109      0.04%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 614218     22.33%     94.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                160061      5.82%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1976611     71.80%     71.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    212      0.01%     71.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                    1052      0.04%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 614146     22.31%     94.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                161054      5.85%    100.00% # attempts to use FU when none available
  system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
  system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            293084      0.04%      0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             795671914     96.55%     96.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               150614      0.02%     96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                125303      0.02%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             18435146      2.24%     98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9402351      1.14%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            292817      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             795957786     96.56%     96.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150640      0.02%     96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                125262      0.02%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.63% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             18413325      2.23%     98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9397431      1.14%    100.00% # Type of FU issued
  system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
  system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              824078412                       # Type of FU issued
-system.cpu.iq.rate                           1.833363                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2750840                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.003338                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2098087999                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         854102050                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    819507550                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 195                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                194                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           56                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              826536078                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      90                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1879985                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              824337261                       # Type of FU issued
+system.cpu.iq.rate                           1.833641                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2753075                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003340                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2098683900                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         854145561                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    819784123                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 216                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                406                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           61                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              826797417                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     102                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1878905                       # Number of loads that had data forwarded from stores
  system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3343174                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14903                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14336                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1767440                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3325389                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14284                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14518                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1760345                       # Number of stores squashed
  system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
  system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2224972                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         73807                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2224613                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         71287                       # Number of times an access to memory failed due to the cache being blocked
  system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 945364                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               205481336                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               9444308                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           830573492                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            185181                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17343194                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10196687                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             711600                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 416792                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               8129202                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14336                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         515306                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       539272                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1054578                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             822459197                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              18034619                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1483642                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 945620                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               205593402                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               9425350                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           830789593                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            184731                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17327061                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10187947                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             714336                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 416093                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               8107674                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14518                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         515540                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       536897                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1052437                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             822725796                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              18017825                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1477345                       # Number of squashed instructions skipped in execute
  system.cpu.iew.exec_swp                             0                       # number of swp insts executed
  system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     27209233                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83289157                       # Number of branches executed
-system.cpu.iew.exec_stores                    9174614                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.829760                       # Inst execution rate
-system.cpu.iew.wb_sent                      821946704                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     819507606                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 640910074                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1050315789                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     27187593                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83308581                       # Number of branches executed
+system.cpu.iew.exec_stores                    9169768                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.830056                       # Inst execution rate
+system.cpu.iew.wb_sent                      822221777                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     819784184                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 641108962                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1050701242                       # num instructions consuming a value
  system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.823194                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.610207                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.823513                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.610172                       # average fanout of values written-back
  system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        24363502                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1055272                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            913280                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    443273616                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.818549                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.675153                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        24183935                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1055789                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            913678                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    443381671                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.819001                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.675688                       # Number of insts commited each cycle
  system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    272516770     61.48%     61.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11195258      2.53%     64.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3583043      0.81%     64.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74523250     16.81%     81.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2432181      0.55%     82.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1605992      0.36%     82.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       951269      0.21%     82.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71009301     16.02%     98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5456552      1.23%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    272578077     61.48%     61.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11201647      2.53%     64.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3542666      0.80%     64.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74562549     16.82%     81.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2432578      0.55%     82.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1609465      0.36%     82.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       914477      0.21%     82.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71049223     16.02%     98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5490989      1.24%    100.00% # Number of insts commited each cycle
  system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
  system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
  system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    443273616                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407812863                       # Number of instructions committed
-system.cpu.commit.committedOps              806114915                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    443381671                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            408006726                       # Number of instructions committed
+system.cpu.commit.committedOps              806511598                       # Number of ops (including micro ops) committed
  system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22429266                       # Number of memory references committed
-system.cpu.commit.loads                      14000019                       # Number of loads committed
-system.cpu.commit.membars                      474889                       # Number of memory barriers committed
-system.cpu.commit.branches                   82168190                       # Number of branches committed
+system.cpu.commit.refs                       22429273                       # Number of memory references committed
+system.cpu.commit.loads                      14001671                       # Number of loads committed
+system.cpu.commit.membars                      475333                       # Number of memory barriers committed
+system.cpu.commit.branches                   82207365                       # Number of branches committed
  system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 734958550                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155635                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       174258      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        783245185     97.16%     97.18% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          144842      0.02%     97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121364      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.int_insts                 735317995                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1155841                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       174216      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        783641693     97.16%     97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          144853      0.02%     97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121563      0.02%     97.22% # Class of committed instruction
  system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
  system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
  system.cpu.commit.op_class_0::FloatCvt              0      0.00%     97.22% # Class of committed instruction
@@ -852,225 +852,225 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% #
  system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
  system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
  system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        14000019      1.74%     98.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8429247      1.05%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        14001671      1.74%     98.96% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8427602      1.04%    100.00% # Class of committed instruction
  system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
  system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         806114915                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5456552                       # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total         806511598                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5490989                       # number cycles where commit BW limit reached
  system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1268217156                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1664635865                       # The number of ROB writes
-system.cpu.timesIdled                          297982                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         2553974                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9810264132                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407812863                       # Number of Instructions Simulated
-system.cpu.committedOps                     806114915                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.102197                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.102197                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.907279                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.907279                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1092267062                       # number of integer regfile reads
-system.cpu.int_regfile_writes               655932610                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        56                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 416128291                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                321990784                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               265578345                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 402863                       # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq        3083726                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3083187                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13776                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13776                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1587489                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46722                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2231                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2231                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       287826                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       287826                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2007150                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6137120                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        34489                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       168921                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8347680                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64225408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    208172445                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1082112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5828032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          279307997                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       61506                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4398693                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.010831                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.103506                       # Request fanout histogram
+system.cpu.rob.rob_reads                   1268507964                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1665044622                       # The number of ROB writes
+system.cpu.timesIdled                          294262                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         2545134                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9802241311                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   408006726                       # Number of Instructions Simulated
+system.cpu.committedOps                     806511598                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.101852                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.101852                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.907563                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.907563                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1092659743                       # number of integer regfile reads
+system.cpu.int_regfile_writes               656162059                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        61                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 416306470                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                322125902                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               265627452                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 402647                       # number of misc regfile writes
+system.cpu.toL2Bus.trans_dist::ReadReq        3066870                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3066328                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13889                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13889                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1584468                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46724                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2232                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2232                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       287069                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       287069                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           10                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1989808                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6126047                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        30798                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       165937                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8312590                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63671040                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207694139                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1011904                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5790912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          278167995                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       58568                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4377947                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.010880                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.103740                       # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            4351052     98.92%     98.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              47641      1.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            4330313     98.91%     98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4              47634      1.09%    100.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4398693                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4081523356                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4377947                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4068281890                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       582000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       567000                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1509600495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1496480643                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3145861612                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3139987945                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      26384476                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      22488486                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     116845140                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     113254360                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements           1003070                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.154171                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             8117984                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1003582                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.089009                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      147599073250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.154171                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996395                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996395                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            994393                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.035216                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             8125717                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            994905                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.167330                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      147627648000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.035216                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996163                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996163                       # Average percentage of cache occupancy
  system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          201                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          141                       # Occupied blocks per task id
  system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10188308                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10188308                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      8117984                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8117984                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8117984                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8117984                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8117984                       # number of overall hits
-system.cpu.icache.overall_hits::total         8117984                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1066696                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1066696                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1066696                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1066696                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1066696                       # number of overall misses
-system.cpu.icache.overall_misses::total       1066696                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14789893561                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14789893561                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14789893561                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14789893561                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14789893561                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14789893561                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9184680                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9184680                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9184680                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9184680                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9184680                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9184680                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116139                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.116139                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.116139                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.116139                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.116139                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.116139                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13865.143922                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13865.143922                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13865.143922                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13865.143922                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13865.143922                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13865.143922                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         6103                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10178850                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10178850                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      8125717                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8125717                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8125717                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8125717                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8125717                       # number of overall hits
+system.cpu.icache.overall_hits::total         8125717                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1058185                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1058185                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1058185                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1058185                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1058185                       # number of overall misses
+system.cpu.icache.overall_misses::total       1058185                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14693875503                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14693875503                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14693875503                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14693875503                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14693875503                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14693875503                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9183902                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9183902                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9183902                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9183902                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9183902                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9183902                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115222                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.115222                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.115222                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.115222                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.115222                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.115222                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13885.923069                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13885.923069                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13885.923069                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13885.923069                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13885.923069                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13885.923069                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         7023                       # number of cycles access was blocked
  system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               266                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               297                       # number of cycles access was blocked
  system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    22.943609                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    23.646465                       # average number of cycles each access was blocked
  system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.icache.fast_writes                       0                       # number of fast writes performed
  system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        63068                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        63068                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        63068                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        63068                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        63068                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        63068                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1003628                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1003628                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1003628                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1003628                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1003628                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1003628                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12143729999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12143729999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12143729999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12143729999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12143729999                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12143729999                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109272                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109272                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109272                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.109272                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109272                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.109272                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12099.831809                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12099.831809                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12099.831809                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12099.831809                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12099.831809                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12099.831809                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        63237                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        63237                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        63237                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        63237                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        63237                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        63237                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       994948                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       994948                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       994948                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       994948                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       994948                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       994948                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12059629101                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12059629101                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12059629101                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12059629101                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12059629101                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12059629101                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108336                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108336                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108336                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.108336                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108336                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.108336                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12120.863704                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12120.863704                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12120.863704                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12120.863704                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12120.863704                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12120.863704                       # average overall mshr miss latency
  system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements        16690                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.006176                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        23588                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs        16704                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     1.412117                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5099387464000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.006176                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.375386                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.375386                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        99931                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        99931                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        23592                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        23592                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.replacements        14092                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.014059                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        26262                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        14107                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     1.861629                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5101924515000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.014059                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.375879                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.375879                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        97491                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        97491                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26263                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        26263                       # number of ReadReq hits
  system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
  system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        23594                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        23594                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        23594                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        23594                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        17581                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        17581                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        17581                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        17581                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        17581                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        17581                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    194939990                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    194939990                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    194939990                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    194939990                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    194939990                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    194939990                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41173                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        41173                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26265                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        26265                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26265                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        26265                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14987                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        14987                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14987                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        14987                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14987                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        14987                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    174073497                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    174073497                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    174073497                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    174073497                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    174073497                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    174073497                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41250                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        41250                       # number of ReadReq accesses(hits+misses)
  system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
  system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41175                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        41175                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41175                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        41175                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.427003                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.427003                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.426982                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.426982                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.426982                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.426982                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11088.105910                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11088.105910                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11088.105910                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11088.105910                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11088.105910                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11088.105910                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41252                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        41252                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41252                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        41252                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.363321                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.363321                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.363304                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.363304                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.363304                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.363304                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11614.966104                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11614.966104                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11614.966104                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11614.966104                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11614.966104                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11614.966104                       # average overall miss latency
  system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1079,85 +1079,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
  system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
  system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         3261                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         3261                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        17581                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        17581                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        17581                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        17581                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        17581                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        17581                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    159752038                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    159752038                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    159752038                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    159752038                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    159752038                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    159752038                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.427003                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.427003                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.426982                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.426982                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.426982                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.426982                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9086.629771                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9086.629771                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9086.629771                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9086.629771                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9086.629771                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9086.629771                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         3303                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         3303                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14987                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14987                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14987                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        14987                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14987                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        14987                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    144083525                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    144083525                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    144083525                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    144083525                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    144083525                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    144083525                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.363321                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.363321                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.363304                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.363304                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.363304                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.363304                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9613.900380                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9613.900380                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9613.900380                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9613.900380                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9613.900380                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9613.900380                       # average overall mshr miss latency
  system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        76771                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    15.789364                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs       114792                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        76787                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.494941                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 197445175000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.789364                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.986835                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.986835                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.replacements        74377                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    15.812457                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       116780                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        74392                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.569792                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.812457                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988279                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988279                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
  system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       463158                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       463158                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       114792                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       114792                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       114792                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       114792                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       114792                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       114792                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        77858                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        77858                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        77858                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        77858                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        77858                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        77858                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    943768714                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    943768714                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    943768714                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    943768714                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    943768714                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    943768714                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       192650                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       192650                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       192650                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       192650                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       192650                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       192650                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.404142                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.404142                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.404142                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.404142                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.404142                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.404142                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12121.666547                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12121.666547                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12121.666547                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12121.666547                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12121.666547                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12121.666547                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses       459926                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       459926                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       116782                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       116782                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       116782                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       116782                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       116782                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       116782                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        75454                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        75454                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        75454                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        75454                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        75454                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        75454                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    927232955                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    927232955                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    927232955                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    927232955                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    927232955                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    927232955                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       192236                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       192236                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       192236                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       192236                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       192236                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       192236                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.392507                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.392507                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.392507                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.392507                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.392507                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.392507                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358                       # average overall miss latency
  system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1166,169 +1166,169 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
  system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
  system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        21599                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        21599                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        77858                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        77858                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        77858                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        77858                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        77858                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        77858                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    787936434                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    787936434                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    787936434                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    787936434                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    787936434                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    787936434                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.404142                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.404142                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.404142                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.404142                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.404142                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.404142                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10120.173059                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10120.173059                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10120.173059                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        21876                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        21876                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        75454                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        75454                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        75454                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        75454                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        75454                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        75454                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    776178235                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    776178235                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    776178235                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    776178235                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    776178235                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    776178235                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.392507                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.392507                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.392507                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.392507                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.392507                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.392507                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862                       # average overall mshr miss latency
  system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1661725                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.996415                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            19139703                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1662237                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.514425                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           1657683                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.996297                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            19131015                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1658195                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.537253                       # Average number of references to valid blocks.
  system.cpu.dcache.tags.warmup_cycle          37454250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.996415                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.996297                       # Average occupied blocks per requestor
  system.cpu.dcache.tags.occ_percent::cpu.data     0.999993                       # Average percentage of cache occupancy
  system.cpu.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
  system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          186                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
  system.cpu.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
  system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88377305                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88377305                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10986051                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10986051                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8085611                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8085611                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        65242                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         65242                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      19071662                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19071662                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19136904                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19136904                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1801162                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1801162                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       334073                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       334073                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       406623                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       406623                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      2135235                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2135235                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2541858                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2541858                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  26563616547                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  26563616547                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  12873735113                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  12873735113                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39437351660                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39437351660                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39437351660                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39437351660                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12787213                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12787213                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8419684                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8419684                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       471865                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       471865                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21206897                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21206897                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21678762                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21678762                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.140856                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.140856                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039678                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.039678                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.861736                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.861736                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.100686                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.100686                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117251                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117251                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14748.044067                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14748.044067                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38535.694633                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38535.694633                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18469.794500                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18469.794500                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15515.167118                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15515.167118                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       377678                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          88314142                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88314142                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10979297                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10979297                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8084679                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8084679                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        64358                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         64358                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      19063976                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19063976                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19128334                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19128334                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1796007                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1796007                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       333248                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       333248                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       406393                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       406393                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2129255                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2129255                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2535648                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2535648                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  26565336178                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  26565336178                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  12842853467                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  12842853467                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39408189645                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39408189645                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39408189645                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39408189645                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12775304                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12775304                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8417927                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8417927                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       470751                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       470751                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21193231                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21193231                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21663982                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21663982                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.140584                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.140584                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039588                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039588                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863287                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.863287                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.100469                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.100469                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.117044                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117044                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18507.970931                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15541.664160                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       378856                       # number of cycles access was blocked
  system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             40377                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             39922                       # number of cycles access was blocked
  system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.353791                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.489905                       # average number of cycles each access was blocked
  system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
  system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1562629                       # number of writebacks
-system.cpu.dcache.writebacks::total           1562629                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       829779                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       829779                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44137                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        44137                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       873916                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       873916                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       873916                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       873916                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       971383                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       971383                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289936                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       289936                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403164                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       403164                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1261319                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1261319                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1664483                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1664483                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12264764518                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12264764518                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11214941849                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11214941849                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5603688502                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5603688502                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23479706367                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23479706367                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29083394869                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29083394869                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97364659500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97364659500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2538935000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2538935000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99903594500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  99903594500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075965                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075965                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034435                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034435                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.854405                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.854405                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059477                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059477                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076779                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076779                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12626.085198                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12626.085198                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38680.749714                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38680.749714                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13899.277966                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13899.277966                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18615.200728                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18615.200728                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.929954                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.929954                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1559289                       # number of writebacks
+system.cpu.dcache.writebacks::total           1559289                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       827651                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       827651                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44088                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        44088                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       871739                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       871739                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       871739                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       871739                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       968356                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       968356                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289160                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       289160                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402927                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402927                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1257516                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1257516                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1660443                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1660443                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12252685521                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12252685521                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11181268784                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11181268784                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5616168251                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5616168251                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23433954305                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23433954305                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29050122556                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29050122556                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97390324000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97390324000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2564320000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2564320000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99954644000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  99954644000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075799                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075799                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034350                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034350                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.855924                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.855924                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059336                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.059336                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076645                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076645                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874                       # average overall mshr miss latency
  system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
  system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
  system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1336,150 +1336,150 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
  system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
  system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
  system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           112646                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64814.554294                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3852282                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           176740                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            21.796322                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           113085                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64818.383323                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3831425                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           176970                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            21.650138                       # Average number of references to valid blocks.
  system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50353.205869                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    15.791697                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.140401                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3275.059967                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11170.356359                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.768329                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000241                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    22.760500                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.143343                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3264.453296                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11098.685488                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.769536                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000347                       # Average percentage of cache occupancy
  system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049973                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.170446                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.988992                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        64094                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          588                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3429                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5695                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54337                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.977997                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         35174951                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        35174951                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        69400                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        13641                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       987138                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1338009                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2408188                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1587489                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1587489                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          311                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          311                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       154123                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       154123                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        69400                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        13641                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       987138                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1492132                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2562311                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        69400                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        13641                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       987138                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1492132                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2562311                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           64                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        16384                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        35861                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        52315                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1456                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1456                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133693                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133693                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           64                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        16384                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       169554                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        186008                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           64                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        16384                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       169554                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       186008                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      5398250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       467000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1244423000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2844994996                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   4095283246                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17419754                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     17419754                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9341540216                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9341540216                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      5398250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       467000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1244423000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  12186535212                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13436823462                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      5398250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       467000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1244423000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  12186535212                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13436823462                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        69464                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        13647                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1003522                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1373870                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2460503                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1587489                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1587489                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1767                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1767                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       287816                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       287816                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        69464                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        13647                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1003522                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1661686                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2748319                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        69464                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        13647                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1003522                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1661686                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2748319                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000440                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016326                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026102                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021262                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.823995                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.823995                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.464509                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.464509                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000440                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016326                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.102037                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.067681                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000440                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016326                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.102037                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.067681                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84347.656250                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77833.333333                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75953.552246                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79333.955997                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 78281.243353                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11964.116758                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11964.116758                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69873.069016                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69873.069016                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84347.656250                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77833.333333                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75953.552246                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71874.064970                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72237.879349                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84347.656250                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77833.333333                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75953.552246                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71874.064970                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72237.879349                       # average overall miss latency
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049812                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.169353                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.989050                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63885                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          634                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3305                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5793                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54091                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.974808                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         35031209                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        35031209                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        68532                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12501                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       978548                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1334624                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2394205                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1584468                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1584468                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          309                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          309                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       153669                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       153669                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        68532                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        12501                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       978548                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1488293                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2547874                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        68532                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        12501                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       978548                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1488293                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2547874                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           75                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        16312                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        35875                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        52269                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1444                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1444                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       133393                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133393                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           75                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            7                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        16312                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       169268                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        185662                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           75                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            7                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        16312                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       169268                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       185662                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      6508500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       560500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1253827000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2884413497                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   4145309497                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16150808                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     16150808                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9313802457                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9313802457                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6508500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       560500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1253827000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  12198215954                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  13459111954                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6508500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       560500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1253827000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  12198215954                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  13459111954                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        68607                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        12508                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       994860                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1370499                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2446474                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1584468                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1584468                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1753                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1753                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       287062                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       287062                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        68607                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        12508                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       994860                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1657561                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2733536                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        68607                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        12508                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       994860                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1657561                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2733536                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001093                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000560                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016396                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026177                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.021365                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.823731                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.823731                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.464684                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.464684                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001093                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000560                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016396                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.102119                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.067920                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001093                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000560                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016396                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.102119                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.067920                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        86780                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80071.428571                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76865.313879                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80401.769951                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 79307.227936                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11184.770083                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11184.770083                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69822.272960                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69822.272960                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        86780                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80071.428571                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76865.313879                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72064.512808                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72492.550732                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        86780                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80071.428571                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76865.313879                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72064.512808                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72492.550732                       # average overall miss latency
  system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1488,99 +1488,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
  system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
  system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       103082                       # number of writebacks
-system.cpu.l2cache.writebacks::total           103082                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks       103196                       # number of writebacks
+system.cpu.l2cache.writebacks::total           103196                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
  system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            7                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
  system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            7                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            3                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
  system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            7                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           64                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16378                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35860                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        52308                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1456                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1456                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133693                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133693                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           64                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16378                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       169553                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       186001                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           64                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16378                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       169553                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       186001                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4610750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       391500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1038765000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2399725996                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3443493246                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14596954                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14596954                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7662739284                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7662739284                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4610750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       391500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1038765000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10062465280                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11106232530                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4610750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       391500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1038765000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10062465280                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11106232530                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89251418000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89251418000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2373087500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2373087500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91624505500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91624505500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000921                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000440                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016321                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026101                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021259                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.823995                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.823995                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464509                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464509                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000921                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000440                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016321                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102037                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.067678                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000921                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000440                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016321                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102037                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.067678                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        65250                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63424.410795                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66919.297156                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65831.101285                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.380495                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.380495                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57315.934896                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57315.934896                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        65250                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63424.410795                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.019988                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59710.606556                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        65250                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63424.410795                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.019988                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59710.606556                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::total            3                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           75                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16310                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35874                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        52266                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1444                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1444                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133393                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133393                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           75                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16310                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       169267                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       185659                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           75                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16310                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       169267                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       185659                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      5579000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       473000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1049198000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2439336749                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3494586749                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14472940                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14472940                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7638617543                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7638617543                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5579000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       473000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1049198000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10077954292                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11133204292                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5579000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       473000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1049198000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10077954292                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11133204292                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89275584000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89275584000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2397149000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2397149000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91672733000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91672733000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001093                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000560                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016394                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026176                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021364                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.823731                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.823731                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464684                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464684                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001093                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000560                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016394                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102118                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.067919                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001093                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000560                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016394                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102118                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.067919                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67571.428571                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64328.510116                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67997.344846                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66861.568687                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10022.811634                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10022.811634                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57264.005930                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57264.005930                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67571.428571                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64328.510116                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59538.801373                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59965.874490                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74386.666667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67571.428571                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64328.510116                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59538.801373                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59965.874490                       # average overall mshr miss latency
  system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
  system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
  system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal

index 61d45995bbe899d1d663bcb99669fa17a5efca8f..95ff094ce0b2add3a125f0c6d2620dc2ecd8f256 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
@@ -4,6 +4,7 @@ BIOS-provided physical RAM map:
   BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)\r
   BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)\r
   BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
+ BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)\r
   BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)\r
  end_pfn_map = 1048576\r
  kernel direct mapping tables up to 100000000 @ 8000-d000\r
@@ -23,18 +24,18 @@ Setting APIC routing to flat
  Processors: 1\r
  swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000\r
  swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000\r
-Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)\r
-Built 1 zonelists.  Total pages: 30612\r
+Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)\r
+Built 1 zonelists.  Total pages: 30610\r
  Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
  Initializing CPU#0\r
  PID hash table entries: 512 (order: 9, 4096 bytes)\r
-time.c: Detected 1999.999 MHz processor.\r
+time.c: Detected 2000.008 MHz processor.\r
  Console: colour dummy device 80x25\r
  console handover: boot [earlyser0] -> real [ttyS0]\r
  Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
  Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
  Checking aperture...\r
-Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)\r
+Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)\r
  Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
  Mount-cache hash table entries: 256\r
  CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
@@ -44,7 +45,7 @@ ACPI: Core revision 20070126
  ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
  ACPI: Unable to load the System Description Tables\r
  Using local APIC timer interrupts.\r
-result 7812524\r
+result 7812560\r
  Detected 7.812 MHz APIC timer.\r
  NET: Registered protocol family 16\r
  PCI: Using configuration type 1\r
@@ -56,6 +57,7 @@ usbcore: registered new interface driver usbfs
  usbcore: registered new interface driver hub\r
  usbcore: registered new device driver usb\r
  PCI: Probing PCI hardware\r
+PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16\r
  PCI-GART: No AMD northbridge found.\r
  NET: Registered protocol family 2\r
  Time: tsc clocksource has been installed.\r
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini

index f38bb864d4eed6beedac2be567b1f44a770918b4..c618cee26ea569371fdf3d4d4050528d053e92a5 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
@@ -263,8 +263,8 @@ transition_latency=100000000
  
  [system.e820_table]
  type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
  eventq_index=0
  
  [system.e820_table.entries0]
@@ -290,6 +290,13 @@ size=133169152
  
  [system.e820_table.entries3]
  type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
  addr=4294901760
  eventq_index=0
  range_type=2
@@ -350,13 +357,13 @@ version=17
  [system.intel_mp_table.base_entries03]
  type=X86IntelMPBus
  bus_id=0
-bus_type=ISA
+bus_type=PCI
  eventq_index=0
  
  [system.intel_mp_table.base_entries04]
  type=X86IntelMPBus
  bus_id=1
-bus_type=PCI
+bus_type=ISA
  eventq_index=0
  
  [system.intel_mp_table.base_entries05]
@@ -366,7 +373,7 @@ dest_io_apic_intin=16
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
  source_bus_irq=16
  trigger=ConformTrigger
  
@@ -377,7 +384,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=0
  trigger=ConformTrigger
  
@@ -388,7 +395,7 @@ dest_io_apic_intin=2
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=0
  trigger=ConformTrigger
  
@@ -399,7 +406,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=1
  trigger=ConformTrigger
  
@@ -410,7 +417,7 @@ dest_io_apic_intin=1
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=1
  trigger=ConformTrigger
  
@@ -421,7 +428,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=3
  trigger=ConformTrigger
  
@@ -432,7 +439,7 @@ dest_io_apic_intin=3
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=3
  trigger=ConformTrigger
  
@@ -443,7 +450,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=4
  trigger=ConformTrigger
  
@@ -454,7 +461,7 @@ dest_io_apic_intin=4
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=4
  trigger=ConformTrigger
  
@@ -465,7 +472,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=5
  trigger=ConformTrigger
  
@@ -476,7 +483,7 @@ dest_io_apic_intin=5
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=5
  trigger=ConformTrigger
  
@@ -487,7 +494,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=6
  trigger=ConformTrigger
  
@@ -498,7 +505,7 @@ dest_io_apic_intin=6
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=6
  trigger=ConformTrigger
  
@@ -509,7 +516,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=7
  trigger=ConformTrigger
  
@@ -520,7 +527,7 @@ dest_io_apic_intin=7
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=7
  trigger=ConformTrigger
  
@@ -531,7 +538,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=8
  trigger=ConformTrigger
  
@@ -542,7 +549,7 @@ dest_io_apic_intin=8
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=8
  trigger=ConformTrigger
  
@@ -553,7 +560,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=9
  trigger=ConformTrigger
  
@@ -564,7 +571,7 @@ dest_io_apic_intin=9
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=9
  trigger=ConformTrigger
  
@@ -575,7 +582,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=10
  trigger=ConformTrigger
  
@@ -586,7 +593,7 @@ dest_io_apic_intin=10
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=10
  trigger=ConformTrigger
  
@@ -597,7 +604,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=11
  trigger=ConformTrigger
  
@@ -608,7 +615,7 @@ dest_io_apic_intin=11
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=11
  trigger=ConformTrigger
  
@@ -619,7 +626,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=12
  trigger=ConformTrigger
  
@@ -630,7 +637,7 @@ dest_io_apic_intin=12
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=12
  trigger=ConformTrigger
  
@@ -641,7 +648,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=13
  trigger=ConformTrigger
  
@@ -652,7 +659,7 @@ dest_io_apic_intin=13
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=13
  trigger=ConformTrigger
  
@@ -663,7 +670,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=14
  trigger=ConformTrigger
  
@@ -674,15 +681,15 @@ dest_io_apic_intin=14
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=14
  trigger=ConformTrigger
  
  [system.intel_mp_table.ext_entries]
  type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
  eventq_index=0
-parent_bus=1
+parent_bus=0
  subtractive_decode=true
  
  [system.intrctrl]
@@ -691,7 +698,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -920,6 +927,7 @@ HeaderType=0
  InterruptLine=14
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=9223372036854775808
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1210,8 +1218,33 @@ pio=system.iobus.master[8]
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -1220,6 +1253,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -1233,19 +1267,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt

index 76fedc0c929deb7ee64ef022af1c0bc57749d916..00990271369cd8554c1b0a07cd62ea0ee3441fc9 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -1,79 +1,79 @@
  
  ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.300439                       # Number of seconds simulated
-sim_ticks                                5300438650000                       # Number of ticks simulated
-final_tick                               5300438650000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.307664                       # Number of seconds simulated
+sim_ticks                                5307664297000                       # Number of ticks simulated
+final_tick                               5307664297000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
  sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 211376                       # Simulator instruction rate (inst/s)
-host_op_rate                                   405302                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10491513446                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 792492                       # Number of bytes of host memory used
-host_seconds                                   505.21                       # Real time elapsed on the host
-sim_insts                                   106789618                       # Number of instructions simulated
-sim_ops                                     204763566                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 131058                       # Simulator instruction rate (inst/s)
+host_op_rate                                   251295                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6508784206                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 839108                       # Number of bytes of host memory used
+host_seconds                                   815.46                       # Real time elapsed on the host
+sim_insts                                   106872831                       # Number of instructions simulated
+sim_ops                                     204921615                       # Number of ops (including micro ops) simulated
  system.voltage_domain.voltage                       1                       # Voltage in Volts
  system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide        35184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       121960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        61480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst        541981136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         38703389                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       101016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        45856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst        470377672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         54942760                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1106370453                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst    541981136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst    470377672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1012358808                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide        35048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker        92784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        39160                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst        533690368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         37117376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       127944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        68056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst        479473072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         56585622                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1107229430                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst    533690368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst    479473072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1013163440                       # Number of instructions bytes read from this memory
  system.physmem.bytes_written::pc.south_bridge.ide      2991104                       # Number of bytes written to this memory
  system.physmem.bytes_written::cpu0.itb.walker           16                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      31533942                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      36447976                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          70973038                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide          814                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker        15245                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         7685                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst          67747642                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data           6493671                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker        12627                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         5732                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst          58797209                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data           9219399                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             142300024                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::cpu0.data      30817575                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data      37205147                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          71013842                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide          797                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker        11598                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         4895                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst          66711296                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           6242247                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker        15993                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         8507                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst          59934134                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data           9480217                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             142409684                       # Number of read requests responded to by this memory
  system.physmem.num_writes::pc.south_bridge.ide        46736                       # Number of write requests responded to by this memory
  system.physmem.num_writes::cpu0.itb.walker            2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data          4739534                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data          5091384                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              9877656                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide         6638                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker         23009                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker         11599                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst           102252129                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             7301922                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker         19058                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          8651                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            88743159                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            10365701                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               208731867                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      102252129                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       88743159                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          190995288                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       564313                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::cpu0.data          4638628                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data          5197709                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              9883075                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         6603                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker         17481                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          7378                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           100550890                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             6993166                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker         24106                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker         12822                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            90335983                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            10661115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               208609544                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      100550890                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       90335983                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          190886873                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       563544                       # Write bandwidth from this memory (bytes/s)
  system.physmem.bw_write::cpu0.itb.walker            3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            5949308                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            6876407                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               13390031                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       570950                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker        23009                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker        11602                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          102252129                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           13251230                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker        19058                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         8651                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           88743159                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           17242108                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              222121898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data            5806240                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            7009702                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               13379490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       570148                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker        17481                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         7381                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          100550890                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12799406                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker        24106                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker        12822                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           90335983                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           17670818                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              221989034                       # Total bandwidth to/from this memory (bytes/s)
  system.physmem.readReqs                             0                       # Number of read requests accepted
  system.physmem.writeReqs                            0                       # Number of write requests accepted
  system.physmem.readBursts                           0                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -253,8 +253,8 @@ system.physmem.readRowHitRate                     nan                       # Ro
  system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
  system.physmem.avgGap                             nan                       # Average gap between requests
  system.physmem.pageHitRate                        nan                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     5123442263750                       # Time in different power states
-system.physmem.memoryStateTime::REF      176993180000                       # Time in different power states
+system.physmem.memoryStateTime::IDLE     5130426623750                       # Time in different power states
+system.physmem.memoryStateTime::REF      177234460000                       # Time in different power states
  system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
  system.physmem.memoryStateTime::ACT                 0                       # Time in different power states
  system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
@@ -266,61 +266,61 @@ system.physmem.readEnergy::0                        0                       # En
  system.physmem.readEnergy::1                        0                       # Energy for read commands per rank (pJ)
  system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
  system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          346198660080                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          346198660080                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          114660947205                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          114660947205                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          3079681479750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          3079681479750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            3540541087035                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            3540541087035                       # Total energy per rank (pJ)
+system.physmem.refreshEnergy::0          346670603760                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          346670603760                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          114817254885                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          114817254885                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          3083879751750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          3083879751750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            3545367610395                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            3545367610395                       # Total energy per rank (pJ)
  system.physmem.averagePower::0             667.971742                       # Core power per rank (mW)
  system.physmem.averagePower::1             667.971742                       # Core power per rank (mW)
  system.ruby.clk_domain.clock                      500                       # Clock period in ticks
  system.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
  system.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
-system.ruby.delayHist::samples               10855969                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.443071                       # delay histogram for all message
-system.ruby.delayHist::stdev                 1.830936                       # delay histogram for all message
-system.ruby.delayHist                    |    10255101     94.47%     94.47% |        1445      0.01%     94.48% |      599037      5.52%    100.00% |         126      0.00%    100.00% |         212      0.00%    100.00% |          12      0.00%    100.00% |          36      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                 10855969                       # delay histogram for all message
+system.ruby.delayHist::samples               10848323                       # delay histogram for all message
+system.ruby.delayHist::mean                  0.443552                       # delay histogram for all message
+system.ruby.delayHist::stdev                 1.831983                       # delay histogram for all message
+system.ruby.delayHist                    |    10247251     94.46%     94.46% |        1323      0.01%     94.47% |      599337      5.52%    100.00% |         144      0.00%    100.00% |         216      0.00%    100.00% |          20      0.00%    100.00% |          32      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                 10848323                       # delay histogram for all message
  system.ruby.outstanding_req_hist::bucket_size            1                      
  system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples    152130131                      
+system.ruby.outstanding_req_hist::samples    152245227                      
  system.ruby.outstanding_req_hist::mean       1.000112                      
  system.ruby.outstanding_req_hist::gmean      1.000078                      
-system.ruby.outstanding_req_hist::stdev      0.010599                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   152113038     99.99%     99.99% |       17093      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total     152130131                      
-system.ruby.latency_hist::bucket_size              32                      
-system.ruby.latency_hist::max_bucket              319                      
-system.ruby.latency_hist::samples           152130130                      
-system.ruby.latency_hist::mean               3.380455                      
-system.ruby.latency_hist::gmean              3.106132                      
-system.ruby.latency_hist::stdev              3.781513                      
-system.ruby.latency_hist                 |   151955103     99.88%     99.88% |         126      0.00%     99.89% |       79786      0.05%     99.94% |       94134      0.06%    100.00% |         979      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total             152130130                      
+system.ruby.outstanding_req_hist::stdev      0.010603                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   152228110     99.99%     99.99% |       17117      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total     152245227                      
+system.ruby.latency_hist::bucket_size              16                      
+system.ruby.latency_hist::max_bucket              159                      
+system.ruby.latency_hist::samples           152245226                      
+system.ruby.latency_hist::mean               3.379322                      
+system.ruby.latency_hist::gmean              3.105966                      
+system.ruby.latency_hist::stdev              3.769964                      
+system.ruby.latency_hist                 |   149590953     98.26%     98.26% |     2481061      1.63%     99.89% |         133      0.00%     99.89% |           0      0.00%     99.89% |       77046      0.05%     99.94% |        1268      0.00%     99.94% |       90138      0.06%    100.00% |        3722      0.00%    100.00% |         854      0.00%    100.00% |          51      0.00%    100.00%
+system.ruby.latency_hist::total             152245226                      
  system.ruby.hit_latency_hist::bucket_size            1                      
  system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples       149475024                      
+system.ruby.hit_latency_hist::samples       149590953                      
  system.ruby.hit_latency_hist::mean                  3                      
  system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   149475024    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total         149475024                      
-system.ruby.miss_latency_hist::bucket_size           32                      
-system.ruby.miss_latency_hist::max_bucket          319                      
-system.ruby.miss_latency_hist::samples        2655106                      
-system.ruby.miss_latency_hist::mean         24.799008                      
-system.ruby.miss_latency_hist::gmean        21.990340                      
-system.ruby.miss_latency_hist::stdev        18.773320                      
-system.ruby.miss_latency_hist            |     2480079     93.41%     93.41% |         126      0.00%     93.41% |       79786      3.01%     96.42% |       94134      3.55%     99.96% |         979      0.04%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total          2655106                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits     10730190                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses       525947                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses     11256137                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits     67423344                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses       324298                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses     67747642                       # Number of cache demand accesses
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   149590953    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total         149590953                      
+system.ruby.miss_latency_hist::bucket_size           16                      
+system.ruby.miss_latency_hist::max_bucket          159                      
+system.ruby.miss_latency_hist::samples        2654273                      
+system.ruby.miss_latency_hist::mean         24.757382                      
+system.ruby.miss_latency_hist::gmean        21.969703                      
+system.ruby.miss_latency_hist::stdev        18.710561                      
+system.ruby.miss_latency_hist            |           0      0.00%      0.00% |     2481061     93.47%     93.47% |         133      0.01%     93.48% |           0      0.00%     93.48% |       77046      2.90%     96.38% |        1268      0.05%     96.43% |       90138      3.40%     99.83% |        3722      0.14%     99.97% |         854      0.03%    100.00% |          51      0.00%    100.00%
+system.ruby.miss_latency_hist::total          2654273                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits     10398035                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses       499335                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses     10897370                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits     66409156                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses       302140                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses     66711296                       # Number of cache demand accesses
  system.cpu_clk_domain.clock                       500                       # Clock period in ticks
  system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
  system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
@@ -331,30 +331,30 @@ system.ruby.l1_cntrl0.prefetcher.hits               0                       # nu
  system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
  system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
  system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.fully_busy_cycles            12                       # cycles for which number of transistions == max transitions
-system.ruby.network.routers0.percent_links_utilized     0.029767                      
-system.ruby.network.routers0.msg_count.Control::0       850245                      
-system.ruby.network.routers0.msg_count.Request_Control::2        42194                      
-system.ruby.network.routers0.msg_count.Response_Data::1       878350                      
-system.ruby.network.routers0.msg_count.Response_Control::1       503571                      
-system.ruby.network.routers0.msg_count.Response_Control::2       500402                      
-system.ruby.network.routers0.msg_count.Writeback_Data::0       294663                      
-system.ruby.network.routers0.msg_count.Writeback_Data::1           77                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0       168221                      
-system.ruby.network.routers0.msg_bytes.Control::0      6801960                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2       337552                      
-system.ruby.network.routers0.msg_bytes.Response_Data::1     63241200                      
-system.ruby.network.routers0.msg_bytes.Response_Control::1      4028568                      
-system.ruby.network.routers0.msg_bytes.Response_Control::2      4003216                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0     21215736                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1         5544                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0      1345768                      
-system.ruby.l1_cntrl1.L1Dcache.demand_hits     13015788                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses      1313354                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses     14329142                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits     58305702                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses       491507                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses     58797209                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.fully_busy_cycles            10                       # cycles for which number of transistions == max transitions
+system.ruby.network.routers0.percent_links_utilized     0.028216                      
+system.ruby.network.routers0.msg_count.Control::0       801475                      
+system.ruby.network.routers0.msg_count.Request_Control::2        41656                      
+system.ruby.network.routers0.msg_count.Response_Data::1       829298                      
+system.ruby.network.routers0.msg_count.Response_Control::1       479862                      
+system.ruby.network.routers0.msg_count.Response_Control::2       476757                      
+system.ruby.network.routers0.msg_count.Writeback_Data::0       284601                      
+system.ruby.network.routers0.msg_count.Writeback_Data::1          103                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0       155150                      
+system.ruby.network.routers0.msg_bytes.Control::0      6411800                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2       333248                      
+system.ruby.network.routers0.msg_bytes.Response_Data::1     59709456                      
+system.ruby.network.routers0.msg_bytes.Response_Control::1      3838896                      
+system.ruby.network.routers0.msg_bytes.Response_Control::2      3814056                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0     20491272                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1         7416                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0      1241200                      
+system.ruby.l1_cntrl1.L1Dcache.demand_hits     13362952                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses      1339474                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses     14702426                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Icache.demand_hits     59420810                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Icache.demand_misses       513324                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Icache.demand_accesses     59934134                       # Number of cache demand accesses
  system.ruby.l1_cntrl1.prefetcher.miss_observed            0                       # number of misses observed
  system.ruby.l1_cntrl1.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
  system.ruby.l1_cntrl1.prefetcher.prefetches_requested            0                       # number of prefetch requests made
@@ -364,111 +364,110 @@ system.ruby.l1_cntrl1.prefetcher.hits               0                       # nu
  system.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
  system.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
  system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.fully_busy_cycles            13                       # cycles for which number of transistions == max transitions
-system.ruby.network.routers1.percent_links_utilized     0.057220                      
-system.ruby.network.routers1.msg_count.Control::0      1804861                      
-system.ruby.network.routers1.msg_count.Request_Control::2        38457                      
-system.ruby.network.routers1.msg_count.Response_Data::1      1828237                      
-system.ruby.network.routers1.msg_count.Response_Control::1      1255902                      
-system.ruby.network.routers1.msg_count.Response_Control::2      1256112                      
-system.ruby.network.routers1.msg_count.Writeback_Data::0       279082                      
-system.ruby.network.routers1.msg_count.Writeback_Data::1          227                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0       940216                      
-system.ruby.network.routers1.msg_bytes.Control::0     14438888                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2       307656                      
-system.ruby.network.routers1.msg_bytes.Response_Data::1    131633064                      
-system.ruby.network.routers1.msg_bytes.Response_Control::1     10047216                      
-system.ruby.network.routers1.msg_bytes.Response_Control::2     10048896                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0     20093904                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1        16344                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0      7521728                      
-system.ruby.l2_cntrl0.L2cache.demand_hits      2431773                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses       223333                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses      2655106                       # Number of cache demand accesses
-system.ruby.l2_cntrl0.fully_busy_cycles             2                       # cycles for which number of transistions == max transitions
-system.ruby.network.routers2.percent_links_utilized     0.091305                      
-system.ruby.network.routers2.msg_count.Control::0      2830007                      
-system.ruby.network.routers2.msg_count.Request_Control::2        78985                      
-system.ruby.network.routers2.msg_count.Response_Data::1      2882064                      
-system.ruby.network.routers2.msg_count.Response_Control::1      1837383                      
-system.ruby.network.routers2.msg_count.Response_Control::2      1756514                      
-system.ruby.network.routers2.msg_count.Writeback_Data::0       573745                      
-system.ruby.network.routers2.msg_count.Writeback_Data::1          304                      
-system.ruby.network.routers2.msg_count.Writeback_Control::0      1108437                      
-system.ruby.network.routers2.msg_bytes.Control::0     22640056                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2       631880                      
-system.ruby.network.routers2.msg_bytes.Response_Data::1    207508608                      
-system.ruby.network.routers2.msg_bytes.Response_Control::1     14699064                      
-system.ruby.network.routers2.msg_bytes.Response_Control::2     14052112                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::0     41309640                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::1        21888                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::0      8867496                      
+system.ruby.l1_cntrl1.fully_busy_cycles            14                       # cycles for which number of transistions == max transitions
+system.ruby.network.routers1.percent_links_utilized     0.058632                      
+system.ruby.network.routers1.msg_count.Control::0      1852798                      
+system.ruby.network.routers1.msg_count.Request_Control::2        38016                      
+system.ruby.network.routers1.msg_count.Response_Data::1      1875931                      
+system.ruby.network.routers1.msg_count.Response_Control::1      1278748                      
+system.ruby.network.routers1.msg_count.Response_Control::2      1279400                      
+system.ruby.network.routers1.msg_count.Writeback_Data::0       289873                      
+system.ruby.network.routers1.msg_count.Writeback_Data::1          222                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0       952884                      
+system.ruby.network.routers1.msg_bytes.Control::0     14822384                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2       304128                      
+system.ruby.network.routers1.msg_bytes.Response_Data::1    135067032                      
+system.ruby.network.routers1.msg_bytes.Response_Control::1     10229984                      
+system.ruby.network.routers1.msg_bytes.Response_Control::2     10235200                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0     20870856                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1        15984                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0      7623072                      
+system.ruby.l2_cntrl0.L2cache.demand_hits      2433243                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses       221030                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses      2654273                       # Number of cache demand accesses
+system.ruby.network.routers2.percent_links_utilized     0.091109                      
+system.ruby.network.routers2.msg_count.Control::0      2827352                      
+system.ruby.network.routers2.msg_count.Request_Control::2        78096                      
+system.ruby.network.routers2.msg_count.Response_Data::1      2878875                      
+system.ruby.network.routers2.msg_count.Response_Control::1      1833514                      
+system.ruby.network.routers2.msg_count.Response_Control::2      1756157                      
+system.ruby.network.routers2.msg_count.Writeback_Data::0       574474                      
+system.ruby.network.routers2.msg_count.Writeback_Data::1          325                      
+system.ruby.network.routers2.msg_count.Writeback_Control::0      1108034                      
+system.ruby.network.routers2.msg_bytes.Control::0     22618816                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2       624768                      
+system.ruby.network.routers2.msg_bytes.Response_Data::1    207279000                      
+system.ruby.network.routers2.msg_bytes.Response_Control::1     14668112                      
+system.ruby.network.routers2.msg_bytes.Response_Control::2     14049256                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::0     41362128                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::1        23400                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::0      8864272                      
  system.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
-system.ruby.dir_cntrl0.memBuffer.memReq        317875                       # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead       175364                       # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite       142511                       # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh       714751                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles       942834                       # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ           46                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ         6611                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls       949491                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq     2.986995                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy       931351                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy         8237                       # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           87                       # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy            8                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait         3151                       # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount |       10282      3.23%      3.23% |        9701      3.05%      6.29% |        9679      3.04%      9.33% |        9712      3.06%     12.39% |       10010      3.15%     15.54% |        9927      3.12%     18.66% |        9854      3.10%     21.76% |        9702      3.05%     24.81% |        9904      3.12%     27.93% |        9752      3.07%     30.99% |        9805      3.08%     34.08% |        9914      3.12%     37.20% |        9948      3.13%     40.33% |        9724      3.06%     43.39% |        9647      3.03%     46.42% |        8750      2.75%     49.17% |       10266      3.23%     52.40% |        9887      3.11%     55.51% |        9844      3.10%     58.61% |        9758      3.07%     61.68% |       10022      3.15%     64.83% |        9879      3.11%     67.94% |        9766      3.07%     71.01% |        9852      3.10%     74.11% |       10073      3.17%     77.28% |        9931      3.12%     80.41% |       10175      3.20%     83.61% |       10769      3.39%     86.99% |       10605      3.34%     90.33% |       10522      3.31%     93.64% |       10506      3.31%     96.95% |        9709      3.05%    100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total       317875                       # Number of accesses per bank
-system.ruby.network.routers3.percent_links_utilized     0.006727                      
-system.ruby.network.routers3.msg_count.Control::0       174901                      
-system.ruby.network.routers3.msg_count.Response_Data::1       273155                      
-system.ruby.network.routers3.msg_count.Response_Control::1       125034                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0        47550                      
+system.ruby.dir_cntrl0.memBuffer.memReq        315612                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead       173522                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite       142090                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh       706808                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles       938252                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ           30                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ         6383                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls       944665                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     2.993121                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy       926705                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy         8329                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy          104                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy            5                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait         3109                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |       10201      3.23%      3.23% |        9660      3.06%      6.29% |        9611      3.05%      9.34% |        9645      3.06%     12.39% |        9963      3.16%     15.55% |        9896      3.14%     18.69% |        9791      3.10%     21.79% |        9613      3.05%     24.83% |        9895      3.14%     27.97% |        9715      3.08%     31.05% |        9712      3.08%     34.12% |        9809      3.11%     37.23% |        9865      3.13%     40.36% |        9619      3.05%     43.41% |        9583      3.04%     46.44% |        8620      2.73%     49.17% |       10251      3.25%     52.42% |        9857      3.12%     55.54% |        9748      3.09%     58.63% |        9683      3.07%     61.70% |        9944      3.15%     64.85% |        9751      3.09%     67.94% |        9685      3.07%     71.01% |        9777      3.10%     74.11% |        9976      3.16%     77.27% |        9827      3.11%     80.38% |       10062      3.19%     83.57% |       10634      3.37%     86.94% |       10589      3.36%     90.30% |       10446      3.31%     93.60% |       10476      3.32%     96.92% |        9708      3.08%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total       315612                       # Number of accesses per bank
+system.ruby.network.routers3.percent_links_utilized     0.006646                      
+system.ruby.network.routers3.msg_count.Control::0       173079                      
+system.ruby.network.routers3.msg_count.Response_Data::1       270344                      
+system.ruby.network.routers3.msg_count.Response_Control::1       121446                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0        47533                      
  system.ruby.network.routers3.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers3.msg_bytes.Control::0      1399208                      
-system.ruby.network.routers3.msg_bytes.Response_Data::1     19667160                      
-system.ruby.network.routers3.msg_bytes.Response_Control::1      1000272                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0       380400                      
+system.ruby.network.routers3.msg_bytes.Control::0      1384632                      
+system.ruby.network.routers3.msg_bytes.Response_Data::1     19464768                      
+system.ruby.network.routers3.msg_bytes.Response_Control::1       971568                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0       380264                      
  system.ruby.network.routers3.msg_bytes.Writeback_Control::1       373888                      
-system.ruby.network.routers4.percent_links_utilized     0.000240                      
-system.ruby.network.routers4.msg_count.Response_Data::1          814                      
-system.ruby.network.routers4.msg_count.Writeback_Control::0        47550                      
+system.ruby.network.routers4.percent_links_utilized     0.000239                      
+system.ruby.network.routers4.msg_count.Response_Data::1          797                      
+system.ruby.network.routers4.msg_count.Writeback_Control::0        47533                      
  system.ruby.network.routers4.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers4.msg_bytes.Response_Data::1        58608                      
-system.ruby.network.routers4.msg_bytes.Writeback_Control::0       380400                      
+system.ruby.network.routers4.msg_bytes.Response_Data::1        57384                      
+system.ruby.network.routers4.msg_bytes.Writeback_Control::0       380264                      
  system.ruby.network.routers4.msg_bytes.Writeback_Control::1       373888                      
-system.ruby.network.routers5.percent_links_utilized     0.037053                      
-system.ruby.network.routers5.msg_count.Control::0      2830007                      
-system.ruby.network.routers5.msg_count.Request_Control::2        80651                      
-system.ruby.network.routers5.msg_count.Response_Data::1      2931310                      
-system.ruby.network.routers5.msg_count.Response_Control::1      1860945                      
-system.ruby.network.routers5.msg_count.Response_Control::2      1756514                      
-system.ruby.network.routers5.msg_count.Writeback_Data::0       573745                      
-system.ruby.network.routers5.msg_count.Writeback_Data::1          304                      
-system.ruby.network.routers5.msg_count.Writeback_Control::0      1155987                      
+system.ruby.network.routers5.percent_links_utilized     0.036969                      
+system.ruby.network.routers5.msg_count.Control::0      2827352                      
+system.ruby.network.routers5.msg_count.Request_Control::2        79672                      
+system.ruby.network.routers5.msg_count.Response_Data::1      2927623                      
+system.ruby.network.routers5.msg_count.Response_Control::1      1856785                      
+system.ruby.network.routers5.msg_count.Response_Control::2      1756157                      
+system.ruby.network.routers5.msg_count.Writeback_Data::0       574474                      
+system.ruby.network.routers5.msg_count.Writeback_Data::1          325                      
+system.ruby.network.routers5.msg_count.Writeback_Control::0      1155567                      
  system.ruby.network.routers5.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers5.msg_bytes.Control::0     22640056                      
-system.ruby.network.routers5.msg_bytes.Request_Control::2       645208                      
-system.ruby.network.routers5.msg_bytes.Response_Data::1    211054320                      
-system.ruby.network.routers5.msg_bytes.Response_Control::1     14887560                      
-system.ruby.network.routers5.msg_bytes.Response_Control::2     14052112                      
-system.ruby.network.routers5.msg_bytes.Writeback_Data::0     41309640                      
-system.ruby.network.routers5.msg_bytes.Writeback_Data::1        21888                      
-system.ruby.network.routers5.msg_bytes.Writeback_Control::0      9247896                      
+system.ruby.network.routers5.msg_bytes.Control::0     22618816                      
+system.ruby.network.routers5.msg_bytes.Request_Control::2       637376                      
+system.ruby.network.routers5.msg_bytes.Response_Data::1    210788856                      
+system.ruby.network.routers5.msg_bytes.Response_Control::1     14854280                      
+system.ruby.network.routers5.msg_bytes.Response_Control::2     14049256                      
+system.ruby.network.routers5.msg_bytes.Writeback_Data::0     41362128                      
+system.ruby.network.routers5.msg_bytes.Writeback_Data::1        23400                      
+system.ruby.network.routers5.msg_bytes.Writeback_Control::0      9244536                      
  system.ruby.network.routers5.msg_bytes.Writeback_Control::1       373888                      
-system.ruby.network.msg_count.Control         8490021                      
-system.ruby.network.msg_count.Request_Control       240287                      
-system.ruby.network.msg_count.Response_Data      8793930                      
-system.ruby.network.msg_count.Response_Control     10852377                      
-system.ruby.network.msg_count.Writeback_Data      1722147                      
-system.ruby.network.msg_count.Writeback_Control      3608169                      
-system.ruby.network.msg_byte.Control         67920168                      
-system.ruby.network.msg_byte.Request_Control      1922296                      
-system.ruby.network.msg_byte.Response_Data    633162960                      
-system.ruby.network.msg_byte.Response_Control     86819016                      
-system.ruby.network.msg_byte.Writeback_Data    123994584                      
-system.ruby.network.msg_byte.Writeback_Control     28865352                      
+system.ruby.network.msg_count.Control         8482056                      
+system.ruby.network.msg_count.Request_Control       237440                      
+system.ruby.network.msg_count.Response_Data      8782868                      
+system.ruby.network.msg_count.Response_Control     10838826                      
+system.ruby.network.msg_count.Writeback_Data      1724397                      
+system.ruby.network.msg_count.Writeback_Control      3606909                      
+system.ruby.network.msg_byte.Control         67856448                      
+system.ruby.network.msg_byte.Request_Control      1899520                      
+system.ruby.network.msg_byte.Response_Data    632366496                      
+system.ruby.network.msg_byte.Response_Control     86710608                      
+system.ruby.network.msg_byte.Writeback_Data    124156584                      
+system.ruby.network.msg_byte.Writeback_Control     28855272                      
  system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
  system.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
  system.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
@@ -481,738 +480,740 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
  system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
  system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
  system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq               858433                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              858433                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               37701                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              37701                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               858552                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              858552                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               37826                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              37826                       # Transaction distribution
  system.iobus.trans_dist::MessageReq              1920                       # Transaction distribution
  system.iobus.trans_dist::MessageResp             1920                       # Transaction distribution
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1700                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1644                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3344                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1704                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1646                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3350                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         5246                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4826                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           88                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          956                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           82                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           38                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       934582                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          984                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          990                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio           90                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14276                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       743206                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14738                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       743208                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          246                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1701984                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1702038                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         5796                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         6216                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           92                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          408                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        33042                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        33054                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          350                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio        33130                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        12392                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio        33142                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        12398                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          250                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         5220                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        90780                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 1796108                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3400                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3288                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6688                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          244                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         5208                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        91208                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 1796596                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3408                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3292                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6700                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         2968                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         2722                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          149                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          478                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           41                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           19                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       467291                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1968                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1980                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio           45                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7138                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1486406                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7369                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1486410                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          492                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1971279                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1971282                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3692                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3938                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           72                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        16521                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        16527                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          700                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio        16565                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6196                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio        16571                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6199                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port        10437                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        54937                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2032904                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy                44000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          488                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port        10413                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        55160                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2033142                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy                53000                       # Layer occupancy (ticks)
  system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
  system.iobus.reqLayer1.occupancy                 6500                       # Layer occupancy (ticks)
  system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy             10297000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy             10251500                       # Layer occupancy (ticks)
  system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               144000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               145500                       # Layer occupancy (ticks)
  system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy              1047500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy              1023500                       # Layer occupancy (ticks)
  system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                96000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy                96500                       # Layer occupancy (ticks)
  system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                56500                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                58000                       # Layer occupancy (ticks)
  system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy             30321000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy             22066000                       # Layer occupancy (ticks)
  system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy            467293000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy            700936500                       # Layer occupancy (ticks)
  system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy              1246000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy              1257500                       # Layer occupancy (ticks)
  system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy            41493500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy            33266500                       # Layer occupancy (ticks)
  system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer11.occupancy                2000                       # Layer occupancy (ticks)
  system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer12.occupancy            23740500                       # Layer occupancy (ticks)
+system.iobus.reqLayer12.occupancy            23678500                       # Layer occupancy (ticks)
  system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
  system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
  system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
  system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               11500                       # Layer occupancy (ticks)
  system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy           469005748                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy           469022392                       # Layer occupancy (ticks)
  system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy             8238216                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy             8247332                       # Layer occupancy (ticks)
  system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy             1328500                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy             1329000                       # Layer occupancy (ticks)
  system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             2422964                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             2431224                       # Layer occupancy (ticks)
  system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy          1790015500                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy          2023353500                       # Layer occupancy (ticks)
  system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy            80920500                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy            64589000                       # Layer occupancy (ticks)
  system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
  system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                     10600877300                       # number of cpu cycles simulated
+system.cpu0.numCycles                     10614251831                       # number of cpu cycles simulated
  system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
  system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   58227397                       # Number of instructions committed
-system.cpu0.committedOps                    111982705                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            104955708                       # Number of integer alu accesses
+system.cpu0.committedInsts                   57435903                       # Number of instructions committed
+system.cpu0.committedOps                    110562263                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            103547988                       # Number of integer alu accesses
  system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     986034                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      9961508                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   104955708                       # number of integer instructions
+system.cpu0.num_func_calls                     961878                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      9838877                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   103547988                       # number of integer instructions
  system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          197725542                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          89196196                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          194836039                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          88035560                       # number of times the integer registers were written
  system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
  system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            60309477                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           43597657                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     12082037                       # number of memory refs
-system.cpu0.num_load_insts                    7332388                       # Number of load instructions
-system.cpu0.num_store_insts                   4749649                       # Number of store instructions
-system.cpu0.num_idle_cycles              10090456434.750097                       # Number of idle cycles
-system.cpu0.num_busy_cycles              510420865.249904                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.048149                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.951851                       # Percentage of idle cycles
-system.cpu0.Branches                         11280989                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass               134403      0.12%      0.12% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 99628506     88.97%     89.09% # Class of executed instruction
-system.cpu0.op_class::IntMult                   83751      0.07%     89.16% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    54749      0.05%     89.21% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     89.21% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7332388      6.55%     95.76% # Class of executed instruction
-system.cpu0.op_class::MemWrite                4749649      4.24%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            59389291                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           43089131                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     11729593                       # number of memory refs
+system.cpu0.num_load_insts                    7080957                       # Number of load instructions
+system.cpu0.num_store_insts                   4648636                       # Number of store instructions
+system.cpu0.num_idle_cycles              10110278190.280666                       # Number of idle cycles
+system.cpu0.num_busy_cycles              503973640.719334                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.047481                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.952519                       # Percentage of idle cycles
+system.cpu0.Branches                         11123723                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass               127569      0.12%      0.12% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 98569733     89.15%     89.27% # Class of executed instruction
+system.cpu0.op_class::IntMult                   84493      0.08%     89.34% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    51490      0.05%     89.39% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     89.39% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7080957      6.40%     95.80% # Class of executed instruction
+system.cpu0.op_class::MemWrite                4648636      4.20%    100.00% # Class of executed instruction
  system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
  system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 111983446                       # Class of executed instruction
+system.cpu0.op_class::total                 110562878                       # Class of executed instruction
  system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
  system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
  system.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu1.numCycles                     10598045368                       # number of cpu cycles simulated
+system.cpu1.numCycles                     10615328594                       # number of cpu cycles simulated
  system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
  system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   48562221                       # Number of instructions committed
-system.cpu1.committedOps                     92780861                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             89101588                       # Number of integer alu accesses
+system.cpu1.committedInsts                   49436928                       # Number of instructions committed
+system.cpu1.committedOps                     94359352                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             90658631                       # Number of integer alu accesses
  system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1756989                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      8282079                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    89101588                       # number of integer instructions
+system.cpu1.num_func_calls                    1782324                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      8422035                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    90658631                       # number of integer instructions
  system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          172887570                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          73678147                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          176032652                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          74963494                       # number of times the integer registers were written
  system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
  system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            51235949                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           33065863                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     14350246                       # number of memory refs
-system.cpu1.num_load_insts                    9231791                       # Number of load instructions
-system.cpu1.num_store_insts                   5118455                       # Number of store instructions
-system.cpu1.num_idle_cycles              10261750383.824707                       # Number of idle cycles
-system.cpu1.num_busy_cycles              336294984.175294                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031732                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968268                       # Percentage of idle cycles
-system.cpu1.Branches                         10643732                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               171960      0.19%      0.19% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 78085090     84.16%     84.35% # Class of executed instruction
-system.cpu1.op_class::IntMult                  100662      0.11%     84.45% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    73682      0.08%     84.53% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     84.53% # Class of executed instruction
-system.cpu1.op_class::MemRead                 9231791      9.95%     94.48% # Class of executed instruction
-system.cpu1.op_class::MemWrite                5118455      5.52%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            52244188                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           33645417                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     14717729                       # number of memory refs
+system.cpu1.num_load_insts                    9492724                       # Number of load instructions
+system.cpu1.num_store_insts                   5225005                       # Number of store instructions
+system.cpu1.num_idle_cycles              10272166234.310064                       # Number of idle cycles
+system.cpu1.num_busy_cycles              343162359.689935                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.032327                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.967673                       # Percentage of idle cycles
+system.cpu1.Branches                         10820224                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               178724      0.19%      0.19% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 79286822     84.03%     84.22% # Class of executed instruction
+system.cpu1.op_class::IntMult                  100062      0.11%     84.32% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    76927      0.08%     84.40% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     84.40% # Class of executed instruction
+system.cpu1.op_class::MemRead                 9492724     10.06%     94.46% # Class of executed instruction
+system.cpu1.op_class::MemWrite                5225005      5.54%    100.00% # Class of executed instruction
  system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
  system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  92781640                       # Class of executed instruction
+system.cpu1.op_class::total                  94360264                       # Class of executed instruction
  system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
  system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.ruby.network.routers0.throttle0.link_utilization     0.038084                      
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::2        42194                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1       838308                      
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1       487492                      
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2       337552                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1     60358176                      
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1      3899936                      
-system.ruby.network.routers0.throttle1.link_utilization     0.021451                      
-system.ruby.network.routers0.throttle1.msg_count.Control::0       850245                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Data::1        40042                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1        16079                      
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2       500402                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0       294663                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1           77                      
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0       168221                      
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0      6801960                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1      2883024                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1       128632                      
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2      4003216                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0     21215736                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1         5544                      
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0      1345768                      
-system.ruby.network.routers1.throttle0.link_utilization     0.082226                      
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::2        38457                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1      1794984                      
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1      1240066                      
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2       307656                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1    129238848                      
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1      9920528                      
-system.ruby.network.routers1.throttle1.link_utilization     0.032215                      
-system.ruby.network.routers1.throttle1.msg_count.Control::0      1804861                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::1        33253                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1        15836                      
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::2      1256112                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0       279082                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1          227                      
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0       940216                      
-system.ruby.network.routers1.throttle1.msg_bytes.Control::0     14438888                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1      2394216                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1       126688                      
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2     10048896                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0     20093904                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1        16344                      
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0      7521728                      
-system.ruby.network.routers2.throttle0.link_utilization     0.059452                      
-system.ruby.network.routers2.throttle0.msg_count.Control::0      2655106                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::1       199764                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::1       120598                      
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::2      1756514                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0       573745                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1          304                      
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0      1108437                      
-system.ruby.network.routers2.throttle0.msg_bytes.Control::0     21240848                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1     14383008                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1       964784                      
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2     14052112                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0     41309640                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1        21888                      
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0      8867496                      
-system.ruby.network.routers2.throttle1.link_utilization     0.123157                      
-system.ruby.network.routers2.throttle1.msg_count.Control::0       174901                      
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::2        78985                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::1      2682300                      
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::1      1716785                      
-system.ruby.network.routers2.throttle1.msg_bytes.Control::0      1399208                      
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2       631880                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1    193125600                      
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1     13734280                      
-system.ruby.network.routers3.throttle0.link_utilization     0.005246                      
-system.ruby.network.routers3.throttle0.msg_count.Control::0       174901                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::1        97440                      
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::1        12789                      
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0        47550                      
-system.ruby.network.routers3.throttle0.msg_bytes.Control::0      1399208                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1      7015680                      
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1       102312                      
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0       380400                      
-system.ruby.network.routers3.throttle1.link_utilization     0.008209                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::1       175715                      
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::1       112245                      
+system.ruby.network.routers0.throttle0.link_utilization     0.035857                      
+system.ruby.network.routers0.throttle0.msg_count.Request_Control::2        41656                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::1       789660                      
+system.ruby.network.routers0.throttle0.msg_count.Response_Control::1       464143                      
+system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2       333248                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1     56855520                      
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1      3713144                      
+system.ruby.network.routers0.throttle1.link_utilization     0.020575                      
+system.ruby.network.routers0.throttle1.msg_count.Control::0       801475                      
+system.ruby.network.routers0.throttle1.msg_count.Response_Data::1        39638                      
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::1        15719                      
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::2       476757                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0       284601                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          103                      
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0       155150                      
+system.ruby.network.routers0.throttle1.msg_bytes.Control::0      6411800                      
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1      2853936                      
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1       125752                      
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2      3814056                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0     20491272                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1         7416                      
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0      1241200                      
+system.ruby.network.routers1.throttle0.link_utilization     0.084264                      
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::2        38016                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::1      1843179                      
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::1      1263070                      
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2       304128                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1    132708888                      
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1     10104560                      
+system.ruby.network.routers1.throttle1.link_utilization     0.033001                      
+system.ruby.network.routers1.throttle1.msg_count.Control::0      1852798                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::1        32752                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::1        15678                      
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::2      1279400                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0       289873                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1          222                      
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0       952884                      
+system.ruby.network.routers1.throttle1.msg_bytes.Control::0     14822384                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1      2358144                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1       125424                      
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2     10235200                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0     20870856                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1        15984                      
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0      7623072                      
+system.ruby.network.routers2.throttle0.link_utilization     0.059288                      
+system.ruby.network.routers2.throttle0.msg_count.Control::0      2654273                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::1       197519                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Control::1       117817                      
+system.ruby.network.routers2.throttle0.msg_count.Response_Control::2      1756157                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0       574474                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1          325                      
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0      1108034                      
+system.ruby.network.routers2.throttle0.msg_bytes.Control::0     21234184                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1     14221368                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1       942536                      
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2     14049256                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0     41362128                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1        23400                      
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0      8864272                      
+system.ruby.network.routers2.throttle1.link_utilization     0.122931                      
+system.ruby.network.routers2.throttle1.msg_count.Control::0       173079                      
+system.ruby.network.routers2.throttle1.msg_count.Request_Control::2        78096                      
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::1      2681356                      
+system.ruby.network.routers2.throttle1.msg_count.Response_Control::1      1715697                      
+system.ruby.network.routers2.throttle1.msg_bytes.Control::0      1384632                      
+system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2       624768                      
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1    193057632                      
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1     13725576                      
+system.ruby.network.routers3.throttle0.link_utilization     0.005184                      
+system.ruby.network.routers3.throttle0.msg_count.Control::0       173079                      
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::1        96468                      
+system.ruby.network.routers3.throttle0.msg_count.Response_Control::1        11755                      
+system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0        47533                      
+system.ruby.network.routers3.throttle0.msg_bytes.Control::0      1384632                      
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1      6945696                      
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1        94040                      
+system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0       380264                      
+system.ruby.network.routers3.throttle1.link_utilization     0.008108                      
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::1       173876                      
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::1       109691                      
  system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1     12651480                      
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1       897960                      
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1     12519072                      
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1       877528                      
  system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1       373888                      
-system.ruby.network.routers4.throttle0.link_utilization     0.000255                      
-system.ruby.network.routers4.throttle0.msg_count.Response_Data::1          814                      
+system.ruby.network.routers4.throttle0.link_utilization     0.000254                      
+system.ruby.network.routers4.throttle0.msg_count.Response_Data::1          797                      
  system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1        58608                      
+system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1        57384                      
  system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1       373888                      
  system.ruby.network.routers4.throttle1.link_utilization     0.000224                      
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0        47550                      
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0       380400                      
-system.ruby.network.routers5.throttle0.link_utilization     0.038084                      
-system.ruby.network.routers5.throttle0.msg_count.Request_Control::2        42194                      
-system.ruby.network.routers5.throttle0.msg_count.Response_Data::1       838308                      
-system.ruby.network.routers5.throttle0.msg_count.Response_Control::1       487492                      
-system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::2       337552                      
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1     60358176                      
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1      3899936                      
-system.ruby.network.routers5.throttle1.link_utilization     0.082226                      
-system.ruby.network.routers5.throttle1.msg_count.Request_Control::2        38457                      
-system.ruby.network.routers5.throttle1.msg_count.Response_Data::1      1794984                      
-system.ruby.network.routers5.throttle1.msg_count.Response_Control::1      1240066                      
-system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2       307656                      
-system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1    129238848                      
-system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1      9920528                      
-system.ruby.network.routers5.throttle2.link_utilization     0.059452                      
-system.ruby.network.routers5.throttle2.msg_count.Control::0      2655106                      
-system.ruby.network.routers5.throttle2.msg_count.Response_Data::1       199764                      
-system.ruby.network.routers5.throttle2.msg_count.Response_Control::1       120598                      
-system.ruby.network.routers5.throttle2.msg_count.Response_Control::2      1756514                      
-system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0       573745                      
-system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1          304                      
-system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0      1108437                      
-system.ruby.network.routers5.throttle2.msg_bytes.Control::0     21240848                      
-system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1     14383008                      
-system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1       964784                      
-system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2     14052112                      
-system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0     41309640                      
-system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1        21888                      
-system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0      8867496                      
-system.ruby.network.routers5.throttle3.link_utilization     0.005246                      
-system.ruby.network.routers5.throttle3.msg_count.Control::0       174901                      
-system.ruby.network.routers5.throttle3.msg_count.Response_Data::1        97440                      
-system.ruby.network.routers5.throttle3.msg_count.Response_Control::1        12789                      
-system.ruby.network.routers5.throttle3.msg_count.Writeback_Control::0        47550                      
-system.ruby.network.routers5.throttle3.msg_bytes.Control::0      1399208                      
-system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1      7015680                      
-system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1       102312                      
-system.ruby.network.routers5.throttle3.msg_bytes.Writeback_Control::0       380400                      
-system.ruby.network.routers5.throttle4.link_utilization     0.000255                      
-system.ruby.network.routers5.throttle4.msg_count.Response_Data::1          814                      
+system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0        47533                      
+system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0       380264                      
+system.ruby.network.routers5.throttle0.link_utilization     0.035857                      
+system.ruby.network.routers5.throttle0.msg_count.Request_Control::2        41656                      
+system.ruby.network.routers5.throttle0.msg_count.Response_Data::1       789660                      
+system.ruby.network.routers5.throttle0.msg_count.Response_Control::1       464143                      
+system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::2       333248                      
+system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1     56855520                      
+system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1      3713144                      
+system.ruby.network.routers5.throttle1.link_utilization     0.084264                      
+system.ruby.network.routers5.throttle1.msg_count.Request_Control::2        38016                      
+system.ruby.network.routers5.throttle1.msg_count.Response_Data::1      1843179                      
+system.ruby.network.routers5.throttle1.msg_count.Response_Control::1      1263070                      
+system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2       304128                      
+system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1    132708888                      
+system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1     10104560                      
+system.ruby.network.routers5.throttle2.link_utilization     0.059288                      
+system.ruby.network.routers5.throttle2.msg_count.Control::0      2654273                      
+system.ruby.network.routers5.throttle2.msg_count.Response_Data::1       197519                      
+system.ruby.network.routers5.throttle2.msg_count.Response_Control::1       117817                      
+system.ruby.network.routers5.throttle2.msg_count.Response_Control::2      1756157                      
+system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0       574474                      
+system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1          325                      
+system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0      1108034                      
+system.ruby.network.routers5.throttle2.msg_bytes.Control::0     21234184                      
+system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1     14221368                      
+system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1       942536                      
+system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2     14049256                      
+system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0     41362128                      
+system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1        23400                      
+system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0      8864272                      
+system.ruby.network.routers5.throttle3.link_utilization     0.005184                      
+system.ruby.network.routers5.throttle3.msg_count.Control::0       173079                      
+system.ruby.network.routers5.throttle3.msg_count.Response_Data::1        96468                      
+system.ruby.network.routers5.throttle3.msg_count.Response_Control::1        11755                      
+system.ruby.network.routers5.throttle3.msg_count.Writeback_Control::0        47533                      
+system.ruby.network.routers5.throttle3.msg_bytes.Control::0      1384632                      
+system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1      6945696                      
+system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1        94040                      
+system.ruby.network.routers5.throttle3.msg_bytes.Writeback_Control::0       380264                      
+system.ruby.network.routers5.throttle4.link_utilization     0.000254                      
+system.ruby.network.routers5.throttle4.msg_count.Response_Data::1          797                      
  system.ruby.network.routers5.throttle4.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1        58608                      
+system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1        57384                      
  system.ruby.network.routers5.throttle4.msg_bytes.Writeback_Control::1       373888                      
  system.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
  system.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples       6093802                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean         0.755007                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev        2.340941                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |     5519285     90.57%     90.57% |         399      0.01%     90.58% |      573737      9.42%     99.99% |         123      0.00%    100.00% |         210      0.00%    100.00% |          12      0.00%    100.00% |          36      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total         6093802                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::samples       6092938                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean         0.756056                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev        2.342480                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |     5517712     90.56%     90.56% |         362      0.01%     90.57% |      574462      9.43%     99.99% |         138      0.00%    100.00% |         212      0.00%    100.00% |          20      0.00%    100.00% |          32      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total         6092938                       # delay histogram for vnet_0
  system.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
  system.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples       4681516                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.044663                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        0.593096                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |     4654718     99.43%     99.43% |         447      0.01%     99.44% |         398      0.01%     99.45% |         648      0.01%     99.46% |       25177      0.54%    100.00% |         123      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           1      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total         4681516                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples       4675713                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.043880                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        0.588229                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |     4649466     99.44%     99.44% |         402      0.01%     99.45% |         397      0.01%     99.46% |         563      0.01%     99.47% |       24746      0.53%    100.00% |         129      0.00%    100.00% |           4      0.00%    100.00% |           2      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total         4675713                       # delay histogram for vnet_1
  system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
  system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples         80651                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         0.000124                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev        0.015747                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |       80646     99.99%     99.99% |           0      0.00%     99.99% |           5      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total           80651                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples         79672                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         0.000276                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev        0.025546                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |       79662     99.99%     99.99% |           0      0.00%     99.99% |           9      0.01%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total           79672                       # delay histogram for vnet_2
  system.ruby.LD.latency_hist::bucket_size           16                      
  system.ruby.LD.latency_hist::max_bucket           159                      
-system.ruby.LD.latency_hist::samples         14920569                      
-system.ruby.LD.latency_hist::mean            4.752955                      
-system.ruby.LD.latency_hist::gmean           3.589881                      
-system.ruby.LD.latency_hist::stdev           6.604009                      
-system.ruby.LD.latency_hist              |    13535034     90.71%     90.71% |     1353292      9.07%     99.78% |          96      0.00%     99.78% |           0      0.00%     99.78% |        9982      0.07%     99.85% |         163      0.00%     99.85% |       20984      0.14%     99.99% |         796      0.01%    100.00% |         200      0.00%    100.00% |          22      0.00%    100.00%
-system.ruby.LD.latency_hist::total           14920569                      
+system.ruby.LD.latency_hist::samples         14929784                      
+system.ruby.LD.latency_hist::mean            4.746137                      
+system.ruby.LD.latency_hist::gmean           3.588822                      
+system.ruby.LD.latency_hist::stdev           6.561595                      
+system.ruby.LD.latency_hist              |    13544851     90.72%     90.72% |     1353763      9.07%     99.79% |          97      0.00%     99.79% |           0      0.00%     99.79% |        9394      0.06%     99.85% |         137      0.00%     99.86% |       20462      0.14%     99.99% |         877      0.01%    100.00% |         177      0.00%    100.00% |          26      0.00%    100.00%
+system.ruby.LD.latency_hist::total           14929784                      
  system.ruby.LD.hit_latency_hist::bucket_size            1                      
  system.ruby.LD.hit_latency_hist::max_bucket            9                      
-system.ruby.LD.hit_latency_hist::samples     13535034                      
+system.ruby.LD.hit_latency_hist::samples     13544851                      
  system.ruby.LD.hit_latency_hist::mean               3                      
  system.ruby.LD.hit_latency_hist::gmean       3.000000                      
-system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |    13535034    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total       13535034                      
+system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |    13544851    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total       13544851                      
  system.ruby.LD.miss_latency_hist::bucket_size           16                      
  system.ruby.LD.miss_latency_hist::max_bucket          159                      
-system.ruby.LD.miss_latency_hist::samples      1385535                      
-system.ruby.LD.miss_latency_hist::mean      21.877250                      
-system.ruby.LD.miss_latency_hist::gmean     20.732182                      
-system.ruby.LD.miss_latency_hist::stdev     12.099590                      
-system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |     1353292     97.67%     97.67% |          96      0.01%     97.68% |           0      0.00%     97.68% |        9982      0.72%     98.40% |         163      0.01%     98.41% |       20984      1.51%     99.93% |         796      0.06%     99.98% |         200      0.01%    100.00% |          22      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total       1385535                      
-system.ruby.ST.latency_hist::bucket_size           32                      
-system.ruby.ST.latency_hist::max_bucket           319                      
-system.ruby.ST.latency_hist::samples          9491428                      
-system.ruby.ST.latency_hist::mean            4.608485                      
-system.ruby.ST.latency_hist::gmean           3.286938                      
-system.ruby.ST.latency_hist::stdev          10.640707                      
-system.ruby.ST.latency_hist              |     9365714     98.68%     98.68% |          17      0.00%     98.68% |       64552      0.68%     99.36% |       60510      0.64%     99.99% |         633      0.01%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.latency_hist::total            9491428                      
+system.ruby.LD.miss_latency_hist::samples      1384933                      
+system.ruby.LD.miss_latency_hist::mean      21.823612                      
+system.ruby.LD.miss_latency_hist::gmean     20.708451                      
+system.ruby.LD.miss_latency_hist::stdev     11.944645                      
+system.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |     1353763     97.75%     97.75% |          97      0.01%     97.76% |           0      0.00%     97.76% |        9394      0.68%     98.43% |         137      0.01%     98.44% |       20462      1.48%     99.92% |         877      0.06%     99.99% |         177      0.01%    100.00% |          26      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total       1384933                      
+system.ruby.ST.latency_hist::bucket_size           16                      
+system.ruby.ST.latency_hist::max_bucket           159                      
+system.ruby.ST.latency_hist::samples          9496728                      
+system.ruby.ST.latency_hist::mean            4.603564                      
+system.ruby.ST.latency_hist::gmean           3.286498                      
+system.ruby.ST.latency_hist::stdev          10.620395                      
+system.ruby.ST.latency_hist              |     9146629     96.31%     96.31% |      225105      2.37%     98.68% |          21      0.00%     98.68% |           0      0.00%     98.68% |       62699      0.66%     99.34% |        1082      0.01%     99.36% |       58016      0.61%     99.97% |        2598      0.03%     99.99% |         554      0.01%    100.00% |          24      0.00%    100.00%
+system.ruby.ST.latency_hist::total            9496728                      
  system.ruby.ST.hit_latency_hist::bucket_size            1                      
  system.ruby.ST.hit_latency_hist::max_bucket            9                      
-system.ruby.ST.hit_latency_hist::samples      9141411                      
+system.ruby.ST.hit_latency_hist::samples      9146629                      
  system.ruby.ST.hit_latency_hist::mean               3                      
  system.ruby.ST.hit_latency_hist::gmean       3.000000                      
-system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |     9141411    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total        9141411                      
-system.ruby.ST.miss_latency_hist::bucket_size           32                      
-system.ruby.ST.miss_latency_hist::max_bucket          319                      
-system.ruby.ST.miss_latency_hist::samples       350017                      
-system.ruby.ST.miss_latency_hist::mean      46.617353                      
-system.ruby.ST.miss_latency_hist::gmean     35.715902                      
-system.ruby.ST.miss_latency_hist::stdev     35.185303                      
-system.ruby.ST.miss_latency_hist         |      224303     64.08%     64.08% |          17      0.00%     64.09% |       64552     18.44%     82.53% |       60510     17.29%     99.82% |         633      0.18%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        350017                      
+system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |     9146629    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total        9146629                      
+system.ruby.ST.miss_latency_hist::bucket_size           16                      
+system.ruby.ST.miss_latency_hist::max_bucket          159                      
+system.ruby.ST.miss_latency_hist::samples       350099                      
+system.ruby.ST.miss_latency_hist::mean      46.498022                      
+system.ruby.ST.miss_latency_hist::gmean     35.614929                      
+system.ruby.ST.miss_latency_hist::stdev     35.174934                      
+system.ruby.ST.miss_latency_hist         |           0      0.00%      0.00% |      225105     64.30%     64.30% |          21      0.01%     64.30% |           0      0.00%     64.30% |       62699     17.91%     82.21% |        1082      0.31%     82.52% |       58016     16.57%     99.09% |        2598      0.74%     99.83% |         554      0.16%     99.99% |          24      0.01%    100.00%
+system.ruby.ST.miss_latency_hist::total        350099                      
  system.ruby.IFETCH.latency_hist::bucket_size           16                      
  system.ruby.IFETCH.latency_hist::max_bucket          159                      
-system.ruby.IFETCH.latency_hist::samples    126544851                      
-system.ruby.IFETCH.latency_hist::mean        3.112747                      
-system.ruby.IFETCH.latency_hist::gmean       3.036514                      
-system.ruby.IFETCH.latency_hist::stdev       1.652226                      
-system.ruby.IFETCH.latency_hist          |   125729046     99.36%     99.36% |      800495      0.63%     99.99% |           4      0.00%     99.99% |           0      0.00%     99.99% |        3856      0.00%     99.99% |          28      0.00%     99.99% |       11079      0.01%    100.00% |         224      0.00%    100.00% |         119      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist::total      126544851                      
+system.ruby.IFETCH.latency_hist::samples    126645430                      
+system.ruby.IFETCH.latency_hist::mean        3.112625                      
+system.ruby.IFETCH.latency_hist::gmean       3.036470                      
+system.ruby.IFETCH.latency_hist::stdev       1.651951                      
+system.ruby.IFETCH.latency_hist          |   125829966     99.36%     99.36% |      800149      0.63%     99.99% |           7      0.00%     99.99% |           0      0.00%     99.99% |        3810      0.00%     99.99% |          27      0.00%     99.99% |       11150      0.01%    100.00% |         208      0.00%    100.00% |         113      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::total      126645430                      
  system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
  system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
-system.ruby.IFETCH.hit_latency_hist::samples    125729046                      
+system.ruby.IFETCH.hit_latency_hist::samples    125829966                      
  system.ruby.IFETCH.hit_latency_hist::mean            3                      
  system.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
-system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   125729046    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist::total    125729046                      
+system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   125829966    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist::total    125829966                      
  system.ruby.IFETCH.miss_latency_hist::bucket_size           16                      
  system.ruby.IFETCH.miss_latency_hist::max_bucket          159                      
-system.ruby.IFETCH.miss_latency_hist::samples       815805                      
-system.ruby.IFETCH.miss_latency_hist::mean    20.488864                      
-system.ruby.IFETCH.miss_latency_hist::gmean    19.593048                      
-system.ruby.IFETCH.miss_latency_hist::stdev    10.934190                      
-system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |      800495     98.12%     98.12% |           4      0.00%     98.12% |           0      0.00%     98.12% |        3856      0.47%     98.60% |          28      0.00%     98.60% |       11079      1.36%     99.96% |         224      0.03%     99.99% |         119      0.01%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total       815805                      
+system.ruby.IFETCH.miss_latency_hist::samples       815464                      
+system.ruby.IFETCH.miss_latency_hist::mean    20.491203                      
+system.ruby.IFETCH.miss_latency_hist::gmean    19.593567                      
+system.ruby.IFETCH.miss_latency_hist::stdev    10.947392                      
+system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |      800149     98.12%     98.12% |           7      0.00%     98.12% |           0      0.00%     98.12% |        3810      0.47%     98.59% |          27      0.00%     98.59% |       11150      1.37%     99.96% |         208      0.03%     99.99% |         113      0.01%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::total       815464                      
  system.ruby.RMW_Read.latency_hist::bucket_size           16                      
  system.ruby.RMW_Read.latency_hist::max_bucket          159                      
-system.ruby.RMW_Read.latency_hist::samples       494298                      
-system.ruby.RMW_Read.latency_hist::mean      5.892257                      
-system.ruby.RMW_Read.latency_hist::gmean     3.949809                      
-system.ruby.RMW_Read.latency_hist::stdev     8.207792                      
-system.ruby.RMW_Read.latency_hist        |      428816     86.75%     86.75% |       64079     12.96%     99.72% |           2      0.00%     99.72% |           0      0.00%     99.72% |         994      0.20%     99.92% |          20      0.00%     99.92% |         365      0.07%    100.00% |          18      0.00%    100.00% |           3      0.00%    100.00% |           1      0.00%    100.00%
-system.ruby.RMW_Read.latency_hist::total       494298                      
+system.ruby.RMW_Read.latency_hist::samples       494062                      
+system.ruby.RMW_Read.latency_hist::mean      5.885454                      
+system.ruby.RMW_Read.latency_hist::gmean     3.946599                      
+system.ruby.RMW_Read.latency_hist::stdev     8.214603                      
+system.ruby.RMW_Read.latency_hist        |      428814     86.79%     86.79% |       63844     12.92%     99.72% |           3      0.00%     99.72% |           0      0.00%     99.72% |         984      0.20%     99.92% |          18      0.00%     99.92% |         359      0.07%     99.99% |          34      0.01%    100.00% |           6      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.latency_hist::total       494062                      
  system.ruby.RMW_Read.hit_latency_hist::bucket_size            1                      
  system.ruby.RMW_Read.hit_latency_hist::max_bucket            9                      
-system.ruby.RMW_Read.hit_latency_hist::samples       428816                      
+system.ruby.RMW_Read.hit_latency_hist::samples       428814                      
  system.ruby.RMW_Read.hit_latency_hist::mean            3                      
  system.ruby.RMW_Read.hit_latency_hist::gmean     3.000000                      
-system.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      428816    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.RMW_Read.hit_latency_hist::total       428816                      
+system.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      428814    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.hit_latency_hist::total       428814                      
  system.ruby.RMW_Read.miss_latency_hist::bucket_size           16                      
  system.ruby.RMW_Read.miss_latency_hist::max_bucket          159                      
-system.ruby.RMW_Read.miss_latency_hist::samples        65482                      
-system.ruby.RMW_Read.miss_latency_hist::mean    24.832519                      
-system.ruby.RMW_Read.miss_latency_hist::gmean    23.924296                      
-system.ruby.RMW_Read.miss_latency_hist::stdev     9.747837                      
-system.ruby.RMW_Read.miss_latency_hist   |           0      0.00%      0.00% |       64079     97.86%     97.86% |           2      0.00%     97.86% |           0      0.00%     97.86% |         994      1.52%     99.38% |          20      0.03%     99.41% |         365      0.56%     99.97% |          18      0.03%     99.99% |           3      0.00%    100.00% |           1      0.00%    100.00%
-system.ruby.RMW_Read.miss_latency_hist::total        65482                      
+system.ruby.RMW_Read.miss_latency_hist::samples        65248                      
+system.ruby.RMW_Read.miss_latency_hist::mean    24.848838                      
+system.ruby.RMW_Read.miss_latency_hist::gmean    23.931357                      
+system.ruby.RMW_Read.miss_latency_hist::stdev     9.830212                      
+system.ruby.RMW_Read.miss_latency_hist   |           0      0.00%      0.00% |       63844     97.85%     97.85% |           3      0.00%     97.85% |           0      0.00%     97.85% |         984      1.51%     99.36% |          18      0.03%     99.39% |         359      0.55%     99.94% |          34      0.05%     99.99% |           6      0.01%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.miss_latency_hist::total        65248                      
  system.ruby.Locked_RMW_Read.latency_hist::bucket_size           16                      
  system.ruby.Locked_RMW_Read.latency_hist::max_bucket          159                      
-system.ruby.Locked_RMW_Read.latency_hist::samples       339492                      
-system.ruby.Locked_RMW_Read.latency_hist::mean     5.237555                      
-system.ruby.Locked_RMW_Read.latency_hist::gmean     3.760998                      
-system.ruby.Locked_RMW_Read.latency_hist::stdev     6.749704                      
-system.ruby.Locked_RMW_Read.latency_hist |      301225     88.73%     88.73% |       37910     11.17%     99.89% |           7      0.00%     99.90% |           0      0.00%     99.90% |         190      0.06%     99.95% |           1      0.00%     99.95% |         148      0.04%    100.00% |          10      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.latency_hist::total       339492                      
+system.ruby.Locked_RMW_Read.latency_hist::samples       339611                      
+system.ruby.Locked_RMW_Read.latency_hist::mean     5.246503                      
+system.ruby.Locked_RMW_Read.latency_hist::gmean     3.765925                      
+system.ruby.Locked_RMW_Read.latency_hist::stdev     6.740886                      
+system.ruby.Locked_RMW_Read.latency_hist |      301082     88.65%     88.65% |       38200     11.25%     99.90% |           5      0.00%     99.90% |           0      0.00%     99.90% |         159      0.05%     99.95% |           4      0.00%     99.95% |         151      0.04%    100.00% |           5      0.00%    100.00% |           4      0.00%    100.00% |           1      0.00%    100.00%
+system.ruby.Locked_RMW_Read.latency_hist::total       339611                      
  system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size            1                      
  system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Read.hit_latency_hist::samples       301225                      
+system.ruby.Locked_RMW_Read.hit_latency_hist::samples       301082                      
  system.ruby.Locked_RMW_Read.hit_latency_hist::mean            3                      
  system.ruby.Locked_RMW_Read.hit_latency_hist::gmean     3.000000                      
-system.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      301225    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.hit_latency_hist::total       301225                      
+system.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      301082    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Read.hit_latency_hist::total       301082                      
  system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size           16                      
  system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket          159                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::samples        38267                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::mean    22.850838                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::gmean    22.292446                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::stdev     7.385228                      
-system.ruby.Locked_RMW_Read.miss_latency_hist |           0      0.00%      0.00% |       37910     99.07%     99.07% |           7      0.02%     99.09% |           0      0.00%     99.09% |         190      0.50%     99.58% |           1      0.00%     99.58% |         148      0.39%     99.97% |          10      0.03%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.miss_latency_hist::total        38267                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::samples        38529                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::mean    22.801630                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::gmean    22.261232                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::stdev     7.273484                      
+system.ruby.Locked_RMW_Read.miss_latency_hist |           0      0.00%      0.00% |       38200     99.15%     99.15% |           5      0.01%     99.16% |           0      0.00%     99.16% |         159      0.41%     99.57% |           4      0.01%     99.58% |         151      0.39%     99.97% |           5      0.01%     99.99% |           4      0.01%    100.00% |           1      0.00%    100.00%
+system.ruby.Locked_RMW_Read.miss_latency_hist::total        38529                      
  system.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
  system.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Write.latency_hist::samples       339492                      
+system.ruby.Locked_RMW_Write.latency_hist::samples       339611                      
  system.ruby.Locked_RMW_Write.latency_hist::mean            3                      
  system.ruby.Locked_RMW_Write.latency_hist::gmean     3.000000                      
-system.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339492    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Write.latency_hist::total       339492                      
+system.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339611    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Write.latency_hist::total       339611                      
  system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size            1                      
  system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Write.hit_latency_hist::samples       339492                      
+system.ruby.Locked_RMW_Write.hit_latency_hist::samples       339611                      
  system.ruby.Locked_RMW_Write.hit_latency_hist::mean            3                      
  system.ruby.Locked_RMW_Write.hit_latency_hist::gmean     3.000000                      
-system.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339492    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Write.hit_latency_hist::total       339492                      
-system.ruby.L1Cache_Controller.Load      |     6084011     40.78%     40.78% |     8836558     59.22%    100.00%
-system.ruby.L1Cache_Controller.Load::total     14920569                      
-system.ruby.L1Cache_Controller.Ifetch    |    67747645     53.54%     53.54% |    58797210     46.46%    100.00%
-system.ruby.L1Cache_Controller.Ifetch::total    126544855                      
-system.ruby.L1Cache_Controller.Store     |     5172126     48.50%     48.50% |     5492584     51.50%    100.00%
-system.ruby.L1Cache_Controller.Store::total     10664710                      
-system.ruby.L1Cache_Controller.Inv       |       16156     50.14%     50.14% |       16063     49.86%    100.00%
-system.ruby.L1Cache_Controller.Inv::total        32219                      
-system.ruby.L1Cache_Controller.L1_Replacement |      823129     31.64%     31.64% |     1778072     68.36%    100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total      2601201                      
-system.ruby.L1Cache_Controller.Fwd_GETX  |       12034     51.06%     51.06% |       11535     48.94%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total        23569                      
-system.ruby.L1Cache_Controller.Fwd_GETS  |       14000     56.32%     56.32% |       10859     43.68%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total        24859                      
+system.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339611    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Write.hit_latency_hist::total       339611                      
+system.ruby.L1Cache_Controller.Load      |     5835258     39.08%     39.08% |     9094526     60.92%    100.00%
+system.ruby.L1Cache_Controller.Load::total     14929784                      
+system.ruby.L1Cache_Controller.Ifetch    |    66711298     52.68%     52.68% |    59934139     47.32%    100.00%
+system.ruby.L1Cache_Controller.Ifetch::total    126645437                      
+system.ruby.L1Cache_Controller.Store     |     5062112     47.44%     47.44% |     5607900     52.56%    100.00%
+system.ruby.L1Cache_Controller.Store::total     10670012                      
+system.ruby.L1Cache_Controller.Inv       |       15822     49.88%     49.88% |       15900     50.12%    100.00%
+system.ruby.L1Cache_Controller.Inv::total        31722                      
+system.ruby.L1Cache_Controller.L1_Replacement |      774576     29.78%     29.78% |     1826560     70.22%    100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total      2601136                      
+system.ruby.L1Cache_Controller.Fwd_GETX  |       12030     51.17%     51.17% |       11480     48.83%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total        23510                      
+system.ruby.L1Cache_Controller.Fwd_GETS  |       13800     56.47%     56.47% |       10636     43.53%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total        24436                      
  system.ruby.L1Cache_Controller.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
  system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total            4                      
-system.ruby.L1Cache_Controller.Data      |         734     41.99%     41.99% |        1014     58.01%    100.00%
-system.ruby.L1Cache_Controller.Data::total         1748                      
-system.ruby.L1Cache_Controller.Data_Exclusive |      250298     19.59%     19.59% |     1027587     80.41%    100.00%
-system.ruby.L1Cache_Controller.Data_Exclusive::total      1277885                      
-system.ruby.L1Cache_Controller.DataS_fromL1 |       10859     43.68%     43.68% |       14004     56.32%    100.00%
-system.ruby.L1Cache_Controller.DataS_fromL1::total        24863                      
-system.ruby.L1Cache_Controller.Data_all_Acks |      576417     43.38%     43.38% |      752379     56.62%    100.00%
-system.ruby.L1Cache_Controller.Data_all_Acks::total      1328796                      
-system.ruby.L1Cache_Controller.Ack       |       11937     54.72%     54.72% |        9877     45.28%    100.00%
-system.ruby.L1Cache_Controller.Ack::total        21814                      
-system.ruby.L1Cache_Controller.Ack_all   |       12671     53.78%     53.78% |       10891     46.22%    100.00%
-system.ruby.L1Cache_Controller.Ack_all::total        23562                      
-system.ruby.L1Cache_Controller.WB_Ack    |      462884     27.52%     27.52% |     1219298     72.48%    100.00%
-system.ruby.L1Cache_Controller.WB_Ack::total      1682182                      
-system.ruby.L1Cache_Controller.NP.Load   |      278313     20.36%     20.36% |     1088632     79.64%    100.00%
-system.ruby.L1Cache_Controller.NP.Load::total      1366945                      
-system.ruby.L1Cache_Controller.NP.Ifetch |      324200     39.75%     39.75% |      491378     60.25%    100.00%
-system.ruby.L1Cache_Controller.NP.Ifetch::total       815578                      
-system.ruby.L1Cache_Controller.NP.Store  |      221640     52.68%     52.68% |      199086     47.32%    100.00%
-system.ruby.L1Cache_Controller.NP.Store::total       420726                      
-system.ruby.L1Cache_Controller.NP.Inv    |        5298     59.26%     59.26% |        3642     40.74%    100.00%
-system.ruby.L1Cache_Controller.NP.Inv::total         8940                      
-system.ruby.L1Cache_Controller.I.Load    |        8389     45.13%     45.13% |       10201     54.87%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total        18590                      
-system.ruby.L1Cache_Controller.I.Ifetch  |          98     43.17%     43.17% |         129     56.83%    100.00%
-system.ruby.L1Cache_Controller.I.Ifetch::total          227                      
-system.ruby.L1Cache_Controller.I.Store   |        5668     50.49%     50.49% |        5558     49.51%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total        11226                      
-system.ruby.L1Cache_Controller.I.L1_Replacement |        8737     52.26%     52.26% |        7980     47.74%    100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total        16717                      
-system.ruby.L1Cache_Controller.S.Load    |      550351     51.54%     51.54% |      517372     48.46%    100.00%
-system.ruby.L1Cache_Controller.S.Load::total      1067723                      
-system.ruby.L1Cache_Controller.S.Ifetch  |    67423344     53.63%     53.63% |    58305702     46.37%    100.00%
-system.ruby.L1Cache_Controller.S.Ifetch::total    125729046                      
-system.ruby.L1Cache_Controller.S.Store   |       11937     54.72%     54.72% |        9877     45.28%    100.00%
-system.ruby.L1Cache_Controller.S.Store::total        21814                      
-system.ruby.L1Cache_Controller.S.Inv     |       10724     46.84%     46.84% |       12170     53.16%    100.00%
-system.ruby.L1Cache_Controller.S.Inv::total        22894                      
-system.ruby.L1Cache_Controller.S.L1_Replacement |      351508     38.96%     38.96% |      550794     61.04%    100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total       902302                      
-system.ruby.L1Cache_Controller.E.Load    |     1120765     29.13%     29.13% |     2726807     70.87%    100.00%
-system.ruby.L1Cache_Controller.E.Load::total      3847572                      
-system.ruby.L1Cache_Controller.E.Store   |       80620     48.39%     48.39% |       85993     51.61%    100.00%
-system.ruby.L1Cache_Controller.E.Store::total       166613                      
-system.ruby.L1Cache_Controller.E.Inv     |          57     70.37%     70.37% |          24     29.63%    100.00%
-system.ruby.L1Cache_Controller.E.Inv::total           81                      
-system.ruby.L1Cache_Controller.E.L1_Replacement |      168221     15.18%     15.18% |      940216     84.82%    100.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement::total      1108437                      
-system.ruby.L1Cache_Controller.E.Fwd_GETX |         207     58.81%     58.81% |         145     41.19%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETX::total          352                      
-system.ruby.L1Cache_Controller.E.Fwd_GETS |        1001     46.45%     46.45% |        1154     53.55%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETS::total         2155                      
-system.ruby.L1Cache_Controller.M.Load    |     4126193     47.87%     47.87% |     4493546     52.13%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total      8619739                      
-system.ruby.L1Cache_Controller.M.Store   |     4852261     48.31%     48.31% |     5192070     51.69%    100.00%
-system.ruby.L1Cache_Controller.M.Store::total     10044331                      
-system.ruby.L1Cache_Controller.M.Inv     |          77     25.33%     25.33% |         227     74.67%    100.00%
-system.ruby.L1Cache_Controller.M.Inv::total          304                      
-system.ruby.L1Cache_Controller.M.L1_Replacement |      294663     51.36%     51.36% |      279082     48.64%    100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total       573745                      
-system.ruby.L1Cache_Controller.M.Fwd_GETX |       11827     50.94%     50.94% |       11390     49.06%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total        23217                      
-system.ruby.L1Cache_Controller.M.Fwd_GETS |       12999     57.25%     57.25% |        9705     42.75%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total        22704                      
+system.ruby.L1Cache_Controller.Data      |         762     41.48%     41.48% |        1075     58.52%    100.00%
+system.ruby.L1Cache_Controller.Data::total         1837                      
+system.ruby.L1Cache_Controller.Data_Exclusive |      234065     18.32%     18.32% |     1043776     81.68%    100.00%
+system.ruby.L1Cache_Controller.Data_Exclusive::total      1277841                      
+system.ruby.L1Cache_Controller.DataS_fromL1 |       10636     43.52%     43.52% |       13804     56.48%    100.00%
+system.ruby.L1Cache_Controller.DataS_fromL1::total        24440                      
+system.ruby.L1Cache_Controller.Data_all_Acks |      544197     40.96%     40.96% |      784524     59.04%    100.00%
+system.ruby.L1Cache_Controller.Data_all_Acks::total      1328721                      
+system.ruby.L1Cache_Controller.Ack       |       11815     55.12%     55.12% |        9619     44.88%    100.00%
+system.ruby.L1Cache_Controller.Ack::total        21434                      
+system.ruby.L1Cache_Controller.Ack_all   |       12577     54.05%     54.05% |       10694     45.95%    100.00%
+system.ruby.L1Cache_Controller.Ack_all::total        23271                      
+system.ruby.L1Cache_Controller.WB_Ack    |      439751     26.14%     26.14% |     1242757     73.86%    100.00%
+system.ruby.L1Cache_Controller.WB_Ack::total      1682508                      
+system.ruby.L1Cache_Controller.NP.Load   |      258938     18.95%     18.95% |     1107616     81.05%    100.00%
+system.ruby.L1Cache_Controller.NP.Load::total      1366554                      
+system.ruby.L1Cache_Controller.NP.Ifetch |      302044     37.05%     37.05% |      513205     62.95%    100.00%
+system.ruby.L1Cache_Controller.NP.Ifetch::total       815249                      
+system.ruby.L1Cache_Controller.NP.Store  |      214618     50.93%     50.93% |      206762     49.07%    100.00%
+system.ruby.L1Cache_Controller.NP.Store::total       421380                      
+system.ruby.L1Cache_Controller.NP.Inv    |        5151     58.52%     58.52% |        3651     41.48%    100.00%
+system.ruby.L1Cache_Controller.NP.Inv::total         8802                      
+system.ruby.L1Cache_Controller.I.Load    |        8341     45.38%     45.38% |       10038     54.62%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total        18379                      
+system.ruby.L1Cache_Controller.I.Ifetch  |          96     44.65%     44.65% |         119     55.35%    100.00%
+system.ruby.L1Cache_Controller.I.Ifetch::total          215                      
+system.ruby.L1Cache_Controller.I.Store   |        5623     50.83%     50.83% |        5439     49.17%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total        11062                      
+system.ruby.L1Cache_Controller.I.L1_Replacement |        8594     51.38%     51.38% |        8133     48.62%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total        16727                      
+system.ruby.L1Cache_Controller.S.Load    |      528432     50.43%     50.43% |      519377     49.57%    100.00%
+system.ruby.L1Cache_Controller.S.Load::total      1047809                      
+system.ruby.L1Cache_Controller.S.Ifetch  |    66409156     52.78%     52.78% |    59420810     47.22%    100.00%
+system.ruby.L1Cache_Controller.S.Ifetch::total    125829966                      
+system.ruby.L1Cache_Controller.S.Store   |       11815     55.12%     55.12% |        9619     44.88%    100.00%
+system.ruby.L1Cache_Controller.S.Store::total        21434                      
+system.ruby.L1Cache_Controller.S.Inv     |       10507     46.67%     46.67% |       12005     53.33%    100.00%
+system.ruby.L1Cache_Controller.S.Inv::total        22512                      
+system.ruby.L1Cache_Controller.S.L1_Replacement |      326231     36.17%     36.17% |      575670     63.83%    100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total       901901                      
+system.ruby.L1Cache_Controller.E.Load    |     1025293     26.46%     26.46% |     2850062     73.54%    100.00%
+system.ruby.L1Cache_Controller.E.Load::total      3875355                      
+system.ruby.L1Cache_Controller.E.Store   |       77623     46.52%     46.52% |       89231     53.48%    100.00%
+system.ruby.L1Cache_Controller.E.Store::total       166854                      
+system.ruby.L1Cache_Controller.E.Inv     |          61     73.49%     73.49% |          22     26.51%    100.00%
+system.ruby.L1Cache_Controller.E.Inv::total           83                      
+system.ruby.L1Cache_Controller.E.L1_Replacement |      155150     14.00%     14.00% |      952884     86.00%    100.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement::total      1108034                      
+system.ruby.L1Cache_Controller.E.Fwd_GETX |         238     54.84%     54.84% |         196     45.16%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETX::total          434                      
+system.ruby.L1Cache_Controller.E.Fwd_GETS |         896     42.85%     42.85% |        1195     57.15%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETS::total         2091                      
+system.ruby.L1Cache_Controller.M.Load    |     4014254     46.56%     46.56% |     4607433     53.44%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total      8621687                      
+system.ruby.L1Cache_Controller.M.Store   |     4752433     47.29%     47.29% |     5296849     52.71%    100.00%
+system.ruby.L1Cache_Controller.M.Store::total     10049282                      
+system.ruby.L1Cache_Controller.M.Inv     |         103     31.69%     31.69% |         222     68.31%    100.00%
+system.ruby.L1Cache_Controller.M.Inv::total          325                      
+system.ruby.L1Cache_Controller.M.L1_Replacement |      284601     49.54%     49.54% |      289873     50.46%    100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total       574474                      
+system.ruby.L1Cache_Controller.M.Fwd_GETX |       11792     51.10%     51.10% |       11284     48.90%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total        23076                      
+system.ruby.L1Cache_Controller.M.Fwd_GETS |       12904     57.75%     57.75% |        9441     42.25%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total        22345                      
  system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
  system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total            4                      
-system.ruby.L1Cache_Controller.IS.Data_Exclusive |      250298     19.59%     19.59% |     1027587     80.41%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1277885                      
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 |       10859     43.68%     43.68% |       14004     56.32%    100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total        24863                      
-system.ruby.L1Cache_Controller.IS.Data_all_Acks |      349843     38.93%     38.93% |      548749     61.07%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total       898592                      
-system.ruby.L1Cache_Controller.IM.Data   |         734     41.99%     41.99% |        1014     58.01%    100.00%
-system.ruby.L1Cache_Controller.IM.Data::total         1748                      
-system.ruby.L1Cache_Controller.IM.Data_all_Acks |      226574     52.67%     52.67% |      203630     47.33%    100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       430204                      
-system.ruby.L1Cache_Controller.SM.Ack    |       11937     54.72%     54.72% |        9877     45.28%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total        21814                      
-system.ruby.L1Cache_Controller.SM.Ack_all |       12671     53.78%     53.78% |       10891     46.22%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total        23562                      
-system.ruby.L1Cache_Controller.M_I.Ifetch |           3     75.00%     75.00% |           1     25.00%    100.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch::total            4                      
-system.ruby.L1Cache_Controller.M_I.WB_Ack |      462884     27.52%     27.52% |     1219298     72.48%    100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total      1682182                      
-system.ruby.L2Cache_Controller.L1_GET_INSTR       815805      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETS        1385683      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX         431953      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_UPGRADE        21814      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX        1682182      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement        95349      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean        12864      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Data        174901      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Ack         110229      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data          23012      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean         2155      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack               1666      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack_all           6687      0.00%      0.00%
-system.ruby.L2Cache_Controller.Unblock          24863      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock      1731651      0.00%      0.00%
-system.ruby.L2Cache_Controller.MEM_Inv           4032      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR        15306      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS        32147      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX       127448      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GET_INSTR       800467      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS        82791      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX         1783      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_UPGRADE        21814      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement          268      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         6335      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.MEM_Inv            3      0.00%      0.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive |      234065     18.32%     18.32% |     1043776     81.68%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1277841                      
+system.ruby.L1Cache_Controller.IS.DataS_fromL1 |       10636     43.52%     43.52% |       13804     56.48%    100.00%
+system.ruby.L1Cache_Controller.IS.DataS_fromL1::total        24440                      
+system.ruby.L1Cache_Controller.IS.Data_all_Acks |      324718     36.16%     36.16% |      573398     63.84%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks::total       898116                      
+system.ruby.L1Cache_Controller.IM.Data   |         762     41.48%     41.48% |        1075     58.52%    100.00%
+system.ruby.L1Cache_Controller.IM.Data::total         1837                      
+system.ruby.L1Cache_Controller.IM.Data_all_Acks |      219479     50.97%     50.97% |      211126     49.03%    100.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       430605                      
+system.ruby.L1Cache_Controller.SM.Ack    |       11815     55.12%     55.12% |        9619     44.88%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total        21434                      
+system.ruby.L1Cache_Controller.SM.Ack_all |       12577     54.05%     54.05% |       10694     45.95%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack_all::total        23271                      
+system.ruby.L1Cache_Controller.M_I.Ifetch |           2     28.57%     28.57% |           5     71.43%    100.00%
+system.ruby.L1Cache_Controller.M_I.Ifetch::total            7                      
+system.ruby.L1Cache_Controller.M_I.WB_Ack |      439751     26.14%     26.14% |     1242757     73.86%    100.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack::total      1682508                      
+system.ruby.L2Cache_Controller.L1_GET_INSTR       815464      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS        1385093      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX         432443      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_UPGRADE        21434      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX        1682508      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement        94918      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean        11837      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Data        173079      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Ack         108223      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data          22674      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean         2091      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack               1576      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack_all           6550      0.00%      0.00%
+system.ruby.L2Cache_Controller.Unblock          24440      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock      1731717      0.00%      0.00%
+system.ruby.L2Cache_Controller.MEM_Inv           2936      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR        15308      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS        31073      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX       126698      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GET_INSTR       800124      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS        82654      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX         1871      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_UPGRADE        21434      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement          224      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         6241      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.MEM_Inv            2      0.00%      0.00%
  system.ruby.L2Cache_Controller.M.L1_GET_INSTR           28      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS      1245738      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX       279152      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement        94920      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean         6421      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.MEM_Inv         1897      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS      1246769      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX       280363      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement        94550      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean         5479      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.MEM_Inv         1319      0.00%      0.00%
  system.ruby.L2Cache_Controller.MT.L1_GET_INSTR            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS        24859      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX        23569      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX      1682182      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement          161      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          108      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.MEM_Inv          116      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack       110229      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.MEM_Inv         1897      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data          229      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS        24436      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX        23510      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX      1682508      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement          144      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          117      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.MEM_Inv          147      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack       108223      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.MEM_Inv         1319      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data          243      0.00%      0.00%
  system.ruby.L2Cache_Controller.MT_I.Ack_all           48      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.MEM_Inv          116      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data           75      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all           33      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack           1395      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all         6335      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack            271      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all          271      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.MEM_Inv            3      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data        32147      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data        15306      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data       127448      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETS          111      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        23597      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS           37      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.MEM_Inv          147      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data           82      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all           35      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack           1350      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all         6241      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack            226      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all          226      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.MEM_Inv            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.L1_GETS            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data        31072      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data        15309      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data       126698      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETS          118      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        23305      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS           42      0.00%      0.00%
  system.ruby.L2Cache_Controller.MT_MB.L1_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1708054      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data        22706      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2155      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data            2      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock        24861      0.00%      0.00%
-system.ruby.DMA_Controller.ReadRequest            814      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1708412      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data        22344      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2090      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data            5      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock        24434      0.00%      0.00%
+system.ruby.DMA_Controller.ReadRequest            797      0.00%      0.00%
  system.ruby.DMA_Controller.WriteRequest         46736      0.00%      0.00%
-system.ruby.DMA_Controller.Data                   814      0.00%      0.00%
+system.ruby.DMA_Controller.Data                   797      0.00%      0.00%
  system.ruby.DMA_Controller.Ack                  46736      0.00%      0.00%
-system.ruby.DMA_Controller.READY.ReadRequest          814      0.00%      0.00%
+system.ruby.DMA_Controller.READY.ReadRequest          797      0.00%      0.00%
  system.ruby.DMA_Controller.READY.WriteRequest        46736      0.00%      0.00%
-system.ruby.DMA_Controller.BUSY_RD.Data           814      0.00%      0.00%
+system.ruby.DMA_Controller.BUSY_RD.Data           797      0.00%      0.00%
  system.ruby.DMA_Controller.BUSY_WR.Ack          46736      0.00%      0.00%
-system.ruby.Directory_Controller.Fetch         174901      0.00%      0.00%
-system.ruby.Directory_Controller.Data           97440      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       175364      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       142511      0.00%      0.00%
-system.ruby.Directory_Controller.DMA_READ          814      0.00%      0.00%
+system.ruby.Directory_Controller.Fetch         173079      0.00%      0.00%
+system.ruby.Directory_Controller.Data           96468      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       173522      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       142090      0.00%      0.00%
+system.ruby.Directory_Controller.DMA_READ          797      0.00%      0.00%
  system.ruby.Directory_Controller.DMA_WRITE        46736      0.00%      0.00%
-system.ruby.Directory_Controller.CleanReplacement        12789      0.00%      0.00%
-system.ruby.Directory_Controller.I.Fetch       174901      0.00%      0.00%
-system.ruby.Directory_Controller.I.DMA_READ          463      0.00%      0.00%
-system.ruby.Directory_Controller.I.DMA_WRITE        45071      0.00%      0.00%
-system.ruby.Directory_Controller.ID.Memory_Data          463      0.00%      0.00%
-system.ruby.Directory_Controller.ID_W.Memory_Ack        45071      0.00%      0.00%
-system.ruby.Directory_Controller.M.Data         95424      0.00%      0.00%
-system.ruby.Directory_Controller.M.DMA_READ          351      0.00%      0.00%
-system.ruby.Directory_Controller.M.DMA_WRITE         1665      0.00%      0.00%
-system.ruby.Directory_Controller.M.CleanReplacement        12789      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data       174901      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack        95424      0.00%      0.00%
-system.ruby.Directory_Controller.M_DRD.Data          351      0.00%      0.00%
-system.ruby.Directory_Controller.M_DRDI.Memory_Ack          351      0.00%      0.00%
-system.ruby.Directory_Controller.M_DWR.Data         1665      0.00%      0.00%
-system.ruby.Directory_Controller.M_DWRI.Memory_Ack         1665      0.00%      0.00%
+system.ruby.Directory_Controller.CleanReplacement        11755      0.00%      0.00%
+system.ruby.Directory_Controller.I.Fetch       173079      0.00%      0.00%
+system.ruby.Directory_Controller.I.DMA_READ          443      0.00%      0.00%
+system.ruby.Directory_Controller.I.DMA_WRITE        45622      0.00%      0.00%
+system.ruby.Directory_Controller.ID.Memory_Data          443      0.00%      0.00%
+system.ruby.Directory_Controller.ID_W.Memory_Ack        45622      0.00%      0.00%
+system.ruby.Directory_Controller.M.Data         95000      0.00%      0.00%
+system.ruby.Directory_Controller.M.DMA_READ          354      0.00%      0.00%
+system.ruby.Directory_Controller.M.DMA_WRITE         1114      0.00%      0.00%
+system.ruby.Directory_Controller.M.CleanReplacement        11755      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data       173079      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack        95000      0.00%      0.00%
+system.ruby.Directory_Controller.M_DRD.Data          354      0.00%      0.00%
+system.ruby.Directory_Controller.M_DRDI.Memory_Ack          354      0.00%      0.00%
+system.ruby.Directory_Controller.M_DWR.Data         1114      0.00%      0.00%
+system.ruby.Directory_Controller.M_DWRI.Memory_Ack         1114      0.00%      0.00%
  
  ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal

index c7dea29716b2e2a6c0cbacf933e303aae4cf664c..cbc69e80a87fb0755e4a7f63e1e0febd57a572d0 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
@@ -4,6 +4,7 @@ BIOS-provided physical RAM map:
   BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)\r
   BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)\r
   BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
+ BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)\r
   BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)\r
  end_pfn_map = 1048576\r
  kernel direct mapping tables up to 100000000 @ 8000-d000\r
@@ -22,9 +23,9 @@ Processor #1
  I/O APIC #2 at 0xFEC00000.\r
  Setting APIC routing to flat\r
  Processors: 2\r
-Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)\r
+Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)\r
  PERCPU: Allocating 34160 bytes of per cpu data\r
-Built 1 zonelists.  Total pages: 30615\r
+Built 1 zonelists.  Total pages: 30613\r
  Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
  Initializing CPU#0\r
  PID hash table entries: 512 (order: 9, 4096 bytes)\r
@@ -35,7 +36,7 @@ console handover: boot [earlyser0] -> real [ttyS0]
  Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
  Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
  Checking aperture...\r
-Memory: 122004k/131072k available (3699k kernel code, 8516k reserved, 1767k data, 248k init)\r
+Memory: 121996k/131072k available (3699k kernel code, 8524k reserved, 1767k data, 248k init)\r
  Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
  Mount-cache hash table entries: 256\r
  CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
@@ -59,6 +60,7 @@ usbcore: registered new interface driver usbfs
  usbcore: registered new interface driver hub\r
  usbcore: registered new device driver usb\r
  PCI: Probing PCI hardware\r
+PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16\r
  PCI-GART: No AMD northbridge found.\r
  NET: Registered protocol family 2\r
  IP route cache hash table entries: 1024 (order: 1, 8192 bytes)\r
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini

index 925d90ad5ff5669a3b1598e231e981e35fdf6d47..2c304759fe39dbf52c8bcd311f10654d1fd506fd 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
@@ -75,7 +75,7 @@ type=Bridge
  clk_domain=system.clk_domain
  delay=50000
  eventq_index=0
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
  req_size=16
  resp_size=16
  master=system.iobus.slave[0]
@@ -114,9 +114,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -353,6 +350,7 @@ do_statistics_insts=true
  dtb=system.cpu2.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -405,7 +403,6 @@ switched_out=true
  system=system
  tracer=system.cpu2.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=
  
@@ -787,8 +784,8 @@ transition_latency=100000000
  
  [system.e820_table]
  type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
  eventq_index=0
  
  [system.e820_table.entries0]
@@ -814,6 +811,13 @@ size=133169152
  
  [system.e820_table.entries3]
  type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
  addr=4294901760
  eventq_index=0
  range_type=2
@@ -862,13 +866,13 @@ version=17
  [system.intel_mp_table.base_entries02]
  type=X86IntelMPBus
  bus_id=0
-bus_type=ISA
+bus_type=PCI
  eventq_index=0
  
  [system.intel_mp_table.base_entries03]
  type=X86IntelMPBus
  bus_id=1
-bus_type=PCI
+bus_type=ISA
  eventq_index=0
  
  [system.intel_mp_table.base_entries04]
@@ -878,7 +882,7 @@ dest_io_apic_intin=16
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
  source_bus_irq=16
  trigger=ConformTrigger
  
@@ -889,7 +893,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=0
  trigger=ConformTrigger
  
@@ -900,7 +904,7 @@ dest_io_apic_intin=2
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=0
  trigger=ConformTrigger
  
@@ -911,7 +915,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=1
  trigger=ConformTrigger
  
@@ -922,7 +926,7 @@ dest_io_apic_intin=1
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=1
  trigger=ConformTrigger
  
@@ -933,7 +937,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=3
  trigger=ConformTrigger
  
@@ -944,7 +948,7 @@ dest_io_apic_intin=3
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=3
  trigger=ConformTrigger
  
@@ -955,7 +959,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=4
  trigger=ConformTrigger
  
@@ -966,7 +970,7 @@ dest_io_apic_intin=4
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=4
  trigger=ConformTrigger
  
@@ -977,7 +981,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=5
  trigger=ConformTrigger
  
@@ -988,7 +992,7 @@ dest_io_apic_intin=5
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=5
  trigger=ConformTrigger
  
@@ -999,7 +1003,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=6
  trigger=ConformTrigger
  
@@ -1010,7 +1014,7 @@ dest_io_apic_intin=6
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=6
  trigger=ConformTrigger
  
@@ -1021,7 +1025,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=7
  trigger=ConformTrigger
  
@@ -1032,7 +1036,7 @@ dest_io_apic_intin=7
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=7
  trigger=ConformTrigger
  
@@ -1043,7 +1047,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=8
  trigger=ConformTrigger
  
@@ -1054,7 +1058,7 @@ dest_io_apic_intin=8
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=8
  trigger=ConformTrigger
  
@@ -1065,7 +1069,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=9
  trigger=ConformTrigger
  
@@ -1076,7 +1080,7 @@ dest_io_apic_intin=9
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=9
  trigger=ConformTrigger
  
@@ -1087,7 +1091,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=10
  trigger=ConformTrigger
  
@@ -1098,7 +1102,7 @@ dest_io_apic_intin=10
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=10
  trigger=ConformTrigger
  
@@ -1109,7 +1113,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=11
  trigger=ConformTrigger
  
@@ -1120,7 +1124,7 @@ dest_io_apic_intin=11
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=11
  trigger=ConformTrigger
  
@@ -1131,7 +1135,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=12
  trigger=ConformTrigger
  
@@ -1142,7 +1146,7 @@ dest_io_apic_intin=12
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=12
  trigger=ConformTrigger
  
@@ -1153,7 +1157,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=13
  trigger=ConformTrigger
  
@@ -1164,7 +1168,7 @@ dest_io_apic_intin=13
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=13
  trigger=ConformTrigger
  
@@ -1175,7 +1179,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=14
  trigger=ConformTrigger
  
@@ -1186,15 +1190,15 @@ dest_io_apic_intin=14
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=14
  trigger=ConformTrigger
  
  [system.intel_mp_table.ext_entries]
  type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
  eventq_index=0
-parent_bus=1
+parent_bus=0
  subtractive_decode=true
  
  [system.intrctrl]
@@ -1203,7 +1207,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -1284,11 +1288,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -1533,6 +1538,7 @@ HeaderType=0
  InterruptLine=14
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=9223372036854775808
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1823,8 +1829,33 @@ pio=system.iobus.master[9]
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -1833,6 +1864,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -1846,19 +1878,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -1888,10 +1927,11 @@ vendor=
  version=
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json

index b8b06f12b68f490480ccbd754071ac89cec74955..3c9f7ff5edeee0602baa6f7646aeff14261c7546 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
@@ -2,39 +2,20 @@
      "name": null, 
      "sim_quantum": 0, 
      "system": {
-        "bridge": {
-            "slave": {
-                "peer": "system.membus.master[0]", 
-                "role": "SLAVE"
-            }, 
-            "name": "bridge", 
-            "req_size": 16, 
-            "delay": 5.0000000000000004e-08, 
-            "eventq_index": 0, 
-            "master": {
-                "peer": "system.iobus.slave[0]", 
-                "role": "MASTER"
-            }, 
-            "cxx_class": "Bridge", 
-            "path": "system.bridge", 
-            "resp_size": 16, 
-            "type": "Bridge"
-        }, 
+        "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9", 
          "l2c": {
-            "assoc": 8, 
-            "mem_side": {
-                "peer": "system.membus.slave[2]", 
-                "role": "MASTER"
-            }, 
-            "cpu_side": {
-                "peer": "system.toL2Bus.master[0]", 
-                "role": "SLAVE"
-            }, 
-            "name": "l2c", 
+            "is_top_level": false, 
+            "prefetcher": null, 
+            "clk_domain": "system.cpu_clk_domain", 
+            "write_buffers": 8, 
+            "response_latency": 20, 
+            "cxx_class": "BaseCache", 
+            "size": 4194304, 
              "tags": {
                  "name": "tags", 
                  "eventq_index": 0, 
                  "hit_latency": 20, 
+                "clk_domain": "system.cpu_clk_domain", 
                  "sequential_access": false, 
                  "assoc": 8, 
                  "cxx_class": "LRU", 
@@ -43,77 +24,56 @@
                  "type": "LRU", 
                  "size": 4194304
              }, 
-            "hit_latency": 20, 
-            "mshrs": 20, 
-            "response_latency": 20, 
-            "is_top_level": false, 
-            "tgts_per_mshr": 12, 
-            "sequential_access": false, 
+            "system": "system", 
              "max_miss_count": 0, 
              "eventq_index": 0, 
+            "mem_side": {
+                "peer": "system.membus.slave[2]", 
+                "role": "MASTER"
+            }, 
+            "mshrs": 20, 
+            "forward_snoops": true, 
+            "hit_latency": 20, 
+            "tgts_per_mshr": 12, 
+            "addr_ranges": [
+                "0:18446744073709551615"
+            ], 
+            "assoc": 8, 
              "prefetch_on_access": false, 
-            "cxx_class": "BaseCache", 
              "path": "system.l2c", 
-            "write_buffers": 8, 
-            "two_queue": false, 
+            "name": "l2c", 
              "type": "BaseCache", 
-            "forward_snoops": true, 
-            "size": 4194304
+            "sequential_access": false, 
+            "cpu_side": {
+                "peer": "system.toL2Bus.master[0]", 
+                "role": "SLAVE"
+            }, 
+            "two_queue": false
          }, 
          "kernel_addr_check": true, 
-        "membus": {
+        "bridge": {
+            "ranges": [
+                "3221225472:4294901760", 
+                "9223372036854775808:11529215046068469759", 
+                "13835058055282163712:18446744073709551615"
+            ], 
              "slave": {
-                "peer": [
-                    "system.apicbridge.master", 
-                    "system.system_port", 
-                    "system.l2c.mem_side", 
-                    "system.cpu0.interrupts.int_master", 
-                    "system.iocache.mem_side"
-                ], 
+                "peer": "system.membus.master[0]", 
                  "role": "SLAVE"
              }, 
-            "name": "membus", 
-            "badaddr_responder": {
-                "ret_data8": 255, 
-                "name": "badaddr_responder", 
-                "pio": {
-                    "peer": "system.membus.default", 
-                    "role": "SLAVE"
-                }, 
-                "ret_bad_addr": true, 
-                "pio_latency": 1.0000000000000001e-07, 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
-                "ret_data64": 18446744073709551615, 
-                "cxx_class": "IsaFake", 
-                "path": "system.membus.badaddr_responder", 
-                "pio_addr": 0, 
-                "type": "IsaFake", 
-                "ret_data16": 65535
-            }, 
-            "default": {
-                "peer": "system.membus.badaddr_responder.pio", 
-                "role": "MASTER"
-            }, 
-            "header_cycles": 1, 
-            "width": 8, 
+            "name": "bridge", 
+            "req_size": 16, 
+            "clk_domain": "system.clk_domain", 
+            "delay": 50000, 
              "eventq_index": 0, 
              "master": {
-                "peer": [
-                    "system.bridge.slave", 
-                    "system.cpu0.interrupts.pio", 
-                    "system.cpu0.interrupts.int_slave", 
-                    "system.physmem.port"
-                ], 
+                "peer": "system.iobus.slave[0]", 
                  "role": "MASTER"
              }, 
-            "cxx_class": "CoherentBus", 
-            "path": "system.membus", 
-            "type": "CoherentBus", 
-            "use_default_range": false
+            "cxx_class": "Bridge", 
+            "path": "system.bridge", 
+            "resp_size": 16, 
+            "type": "Bridge"
          }, 
          "iobus": {
              "slave": {
@@ -129,6 +89,7 @@
                  "peer": "system.pc.pciconfig.pio", 
                  "role": "MASTER"
              }, 
+            "clk_domain": "system.clk_domain", 
              "header_cycles": 1, 
              "width": 8, 
              "eventq_index": 0, 
@@ -156,68 +117,23 @@
                  ], 
                  "role": "MASTER"
              }, 
-            "cxx_class": "NoncoherentBus", 
+            "cxx_class": "NoncoherentXBar", 
              "path": "system.iobus", 
-            "type": "NoncoherentBus", 
+            "type": "NoncoherentXBar", 
              "use_default_range": false
          }, 
-        "physmem": [
-            {
-                "static_frontend_latency": 1e-08, 
-                "tRFC": 2.6e-07, 
-                "activation_limit": 4, 
-                "tWTR": 7.500000000000001e-09, 
-                "write_low_thresh_perc": 50, 
-                "channels": 1, 
-                "write_buffer_size": 64, 
-                "device_bus_width": 8, 
-                "write_high_thresh_perc": 85, 
-                "cxx_class": "DRAMCtrl", 
-                "null": false, 
-                "port": {
-                    "peer": "system.membus.master[3]", 
-                    "role": "SLAVE"
-                }, 
-                "in_addr_map": true, 
-                "tRRD": 6.000000000000001e-09, 
-                "tRTW": 2.5e-09, 
-                "max_accesses_per_row": 16, 
-                "burst_length": 8, 
-                "tRTP": 7.500000000000001e-09, 
-                "tWR": 1.5000000000000002e-08, 
-                "eventq_index": 0, 
-                "static_backend_latency": 1e-08, 
-                "banks_per_rank": 8, 
-                "addr_mapping": "RoRaBaChCo", 
-                "tRCD": 1.375e-08, 
-                "type": "DRAMCtrl", 
-                "min_writes_per_switch": 16, 
-                "ranks_per_channel": 2, 
-                "page_policy": "open_adaptive", 
-                "tCL": 1.375e-08, 
-                "read_buffer_size": 32, 
-                "conf_table_reported": true, 
-                "tCK": 1.25e-09, 
-                "tRAS": 3.5e-08, 
-                "tBURST": 5e-09, 
-                "path": "system.physmem", 
-                "devices_per_rank": 8, 
-                "name": "physmem", 
-                "tXAW": 3.0000000000000004e-08, 
-                "tREFI": 7.8e-06, 
-                "mem_sched_policy": "frfcfs", 
-                "tRP": 1.375e-08, 
-                "device_rowbuffer_size": 1024
-            }
-        ], 
          "apicbridge": {
+            "ranges": [
+                "11529215046068469760:11529215046068473855"
+            ], 
              "slave": {
                  "peer": "system.iobus.master[0]", 
                  "role": "SLAVE"
              }, 
              "name": "apicbridge", 
              "req_size": 16, 
-            "delay": 5.0000000000000004e-08, 
+            "clk_domain": "system.clk_domain", 
+            "delay": 50000, 
              "eventq_index": 0, 
              "master": {
                  "peer": "system.membus.slave[0]", 
@@ -228,23 +144,26 @@
              "resp_size": 16, 
              "type": "Bridge"
          }, 
+        "symbolfile": "", 
+        "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", 
          "intel_mp_table": {
              "oem_table_addr": 0, 
              "name": "intel_mp_table", 
              "ext_entries": [
                  {
-                    "parent_bus": 1, 
+                    "parent_bus": 0, 
                      "name": "ext_entries", 
                      "type": "X86IntelMPBusHierarchy", 
                      "subtractive_decode": true, 
                      "eventq_index": 0, 
                      "cxx_class": "X86ISA::IntelMP::BusHierarchy", 
                      "path": "system.intel_mp_table.ext_entries", 
-                    "bus_id": 0
+                    "bus_id": 1
                  }
              ], 
-            "spec_rev": 4, 
+            "oem_id": "", 
              "eventq_index": 0, 
+            "spec_rev": 4, 
              "base_entries": [
                  {
                      "enable": true, 
@@ -273,6 +192,7 @@
                      "id": 1
                  }, 
                  {
+                    "bus_type": "PCI", 
                      "name": "base_entries02", 
                      "type": "X86IntelMPBus", 
                      "eventq_index": 0, 
@@ -281,6 +201,7 @@
                      "bus_id": 0
                  }, 
                  {
+                    "bus_type": "ISA", 
                      "name": "base_entries03", 
                      "type": "X86IntelMPBus", 
                      "eventq_index": 0, 
@@ -295,7 +216,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 1, 
+                    "source_bus_id": 0, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 16, 
                      "path": "system.intel_mp_table.base_entries04", 
@@ -309,7 +230,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries05", 
@@ -323,7 +244,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 2, 
                      "path": "system.intel_mp_table.base_entries06", 
@@ -337,7 +258,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries07", 
@@ -351,7 +272,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 1, 
                      "path": "system.intel_mp_table.base_entries08", 
@@ -365,7 +286,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries09", 
@@ -379,7 +300,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 3, 
                      "path": "system.intel_mp_table.base_entries10", 
@@ -393,7 +314,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries11", 
@@ -407,7 +328,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 4, 
                      "path": "system.intel_mp_table.base_entries12", 
@@ -421,7 +342,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries13", 
@@ -435,7 +356,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 5, 
                      "path": "system.intel_mp_table.base_entries14", 
@@ -449,7 +370,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries15", 
@@ -463,7 +384,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 6, 
                      "path": "system.intel_mp_table.base_entries16", 
@@ -477,7 +398,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries17", 
@@ -491,7 +412,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 7, 
                      "path": "system.intel_mp_table.base_entries18", 
@@ -505,7 +426,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries19", 
@@ -519,7 +440,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 8, 
                      "path": "system.intel_mp_table.base_entries20", 
@@ -533,7 +454,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries21", 
@@ -547,7 +468,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 9, 
                      "path": "system.intel_mp_table.base_entries22", 
@@ -561,7 +482,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries23", 
@@ -575,7 +496,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 10, 
                      "path": "system.intel_mp_table.base_entries24", 
@@ -589,7 +510,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries25", 
@@ -603,7 +524,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 11, 
                      "path": "system.intel_mp_table.base_entries26", 
@@ -617,7 +538,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries27", 
@@ -631,7 +552,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 12, 
                      "path": "system.intel_mp_table.base_entries28", 
@@ -645,7 +566,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries29", 
@@ -659,7 +580,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 13, 
                      "path": "system.intel_mp_table.base_entries30", 
@@ -673,7 +594,7 @@
                      "interrupt_type": "ExtInt", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 0, 
                      "path": "system.intel_mp_table.base_entries31", 
@@ -687,7 +608,7 @@
                      "interrupt_type": "INT", 
                      "trigger": "ConformTrigger", 
                      "eventq_index": 0, 
-                    "source_bus_id": 0, 
+                    "source_bus_id": 1, 
                      "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
                      "dest_io_apic_intin": 14, 
                      "path": "system.intel_mp_table.base_entries32", 
@@ -699,55 +620,183 @@
              "path": "system.intel_mp_table", 
              "type": "X86IntelMPConfigTable", 
              "local_apic": 4276092928, 
-            "oem_table_size": 0
+            "oem_table_size": 0, 
+            "product_id": ""
          }, 
          "cxx_class": "LinuxX86System", 
          "load_offset": 0, 
-        "work_end_ckpt_count": 0, 
-        "smbios_table": {
-            "name": "smbios_table", 
-            "structures": [
-                {
-                    "major": 0, 
-                    "name": "structures", 
-                    "emb_cont_firmware_major": 0, 
-                    "rom_size": 0, 
-                    "starting_addr_segment": 0, 
-                    "emb_cont_firmware_minor": 0, 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::SMBios::BiosInformation", 
-                    "path": "system.smbios_table.structures", 
-                    "type": "X86SMBiosBiosInformation", 
-                    "minor": 0
-                }
+        "iocache": {
+            "is_top_level": true, 
+            "prefetcher": null, 
+            "clk_domain": "system.clk_domain", 
+            "write_buffers": 8, 
+            "response_latency": 50, 
+            "cxx_class": "BaseCache", 
+            "size": 1024, 
+            "tags": {
+                "name": "tags", 
+                "eventq_index": 0, 
+                "hit_latency": 50, 
+                "clk_domain": "system.clk_domain", 
+                "sequential_access": false, 
+                "assoc": 8, 
+                "cxx_class": "LRU", 
+                "path": "system.iocache.tags", 
+                "block_size": 64, 
+                "type": "LRU", 
+                "size": 1024
+            }, 
+            "system": "system", 
+            "max_miss_count": 0, 
+            "eventq_index": 0, 
+            "mem_side": {
+                "peer": "system.membus.slave[4]", 
+                "role": "MASTER"
+            }, 
+            "mshrs": 20, 
+            "forward_snoops": false, 
+            "hit_latency": 50, 
+            "tgts_per_mshr": 12, 
+            "addr_ranges": [
+                "0:134217727"
              ], 
-            "major_version": 2, 
-            "minor_version": 5, 
+            "assoc": 8, 
+            "prefetch_on_access": false, 
+            "path": "system.iocache", 
+            "name": "iocache", 
+            "type": "BaseCache", 
+            "sequential_access": false, 
+            "cpu_side": {
+                "peer": "system.iobus.master[18]", 
+                "role": "SLAVE"
+            }, 
+            "two_queue": false
+        }, 
+        "intel_mp_pointer": {
+            "imcr_present": true, 
+            "name": "intel_mp_pointer", 
+            "spec_rev": 4, 
              "eventq_index": 0, 
-            "cxx_class": "X86ISA::SMBios::SMBiosTable", 
-            "path": "system.smbios_table", 
-            "type": "X86SMBiosSMBiosTable"
+            "cxx_class": "X86ISA::IntelMP::FloatingPointer", 
+            "path": "system.intel_mp_pointer", 
+            "type": "X86IntelMPFloatingPointer", 
+            "default_config": 0
+        }, 
+        "memories": [
+            "system.physmem"
+        ], 
+        "acpi_description_table_pointer": {
+            "name": "acpi_description_table_pointer", 
+            "cxx_class": "X86ISA::ACPI::RSDP", 
+            "xsdt": {
+                "oem_table_id": "", 
+                "name": "xsdt", 
+                "entries": [], 
+                "creator_revision": 0, 
+                "creator_id": "", 
+                "oem_id": "", 
+                "eventq_index": 0, 
+                "cxx_class": "X86ISA::ACPI::XSDT", 
+                "path": "system.acpi_description_table_pointer.xsdt", 
+                "oem_revision": 0, 
+                "type": "X86ACPIXSDT"
+            }, 
+            "rsdt": null, 
+            "eventq_index": 0, 
+            "oem_id": "", 
+            "path": "system.acpi_description_table_pointer", 
+            "type": "X86ACPIRSDP", 
+            "revision": 2
          }, 
-        "work_begin_ckpt_count": 0, 
          "clk_domain": {
              "name": "clk_domain", 
+            "clock": [
+                1000
+            ], 
              "init_perf_level": 0, 
+            "voltage_domain": "system.voltage_domain", 
              "eventq_index": 0, 
              "cxx_class": "SrcClockDomain", 
              "path": "system.clk_domain", 
              "type": "SrcClockDomain", 
              "domain_id": -1
          }, 
+        "mem_ranges": [
+            "0:134217727"
+        ], 
+        "membus": {
+            "default": {
+                "peer": "system.membus.badaddr_responder.pio", 
+                "role": "MASTER"
+            }, 
+            "slave": {
+                "peer": [
+                    "system.apicbridge.master", 
+                    "system.system_port", 
+                    "system.l2c.mem_side", 
+                    "system.cpu0.interrupts.int_master", 
+                    "system.iocache.mem_side"
+                ], 
+                "role": "SLAVE"
+            }, 
+            "name": "membus", 
+            "badaddr_responder": {
+                "system": "system", 
+                "ret_data8": 255, 
+                "name": "badaddr_responder", 
+                "warn_access": "", 
+                "pio": {
+                    "peer": "system.membus.default", 
+                    "role": "SLAVE"
+                }, 
+                "ret_bad_addr": true, 
+                "pio_latency": 100000, 
+                "clk_domain": "system.clk_domain", 
+                "fake_mem": false, 
+                "pio_size": 8, 
+                "ret_data32": 4294967295, 
+                "eventq_index": 0, 
+                "update_data": false, 
+                "ret_data64": 18446744073709551615, 
+                "cxx_class": "IsaFake", 
+                "path": "system.membus.badaddr_responder", 
+                "pio_addr": 0, 
+                "type": "IsaFake", 
+                "ret_data16": 65535
+            }, 
+            "snoop_filter": null, 
+            "clk_domain": "system.clk_domain", 
+            "header_cycles": 1, 
+            "system": "system", 
+            "width": 8, 
+            "eventq_index": 0, 
+            "master": {
+                "peer": [
+                    "system.bridge.slave", 
+                    "system.cpu0.interrupts.pio", 
+                    "system.cpu0.interrupts.int_slave", 
+                    "system.physmem.port"
+                ], 
+                "role": "MASTER"
+            }, 
+            "cxx_class": "CoherentXBar", 
+            "path": "system.membus", 
+            "type": "CoherentXBar", 
+            "use_default_range": false
+        }, 
          "pc": {
              "fake_com_4": {
+                "system": "system", 
                  "ret_data8": 255, 
                  "name": "fake_com_4", 
+                "warn_access": "", 
                  "pio": {
                      "peer": "system.iobus.master[16]", 
                      "role": "SLAVE"
                  }, 
                  "ret_bad_addr": false, 
-                "pio_latency": 1.0000000000000001e-07, 
+                "pio_latency": 100000, 
+                "clk_domain": "system.clk_domain", 
                  "fake_mem": false, 
                  "pio_size": 8, 
                  "ret_data32": 4294967295, 
@@ -767,7 +816,10 @@
                      "role": "SLAVE"
                  }, 
                  "bus": 0, 
-                "pio_latency": 3.0000000000000004e-08, 
+                "pio_latency": 30000, 
+                "clk_domain": "system.clk_domain", 
+                "system": "system", 
+                "platform": "system.pc", 
                  "eventq_index": 0, 
                  "cxx_class": "PciConfigAll", 
                  "path": "system.pc.pciconfig", 
@@ -776,14 +828,17 @@
                  "size": 16777216
              }, 
              "fake_com_2": {
+                "system": "system", 
                  "ret_data8": 255, 
                  "name": "fake_com_2", 
+                "warn_access": "", 
                  "pio": {
                      "peer": "system.iobus.master[14]", 
                      "role": "SLAVE"
                  }, 
                  "ret_bad_addr": false, 
-                "pio_latency": 1.0000000000000001e-07, 
+                "pio_latency": 100000, 
+                "clk_domain": "system.clk_domain", 
                  "fake_mem": false, 
                  "pio_size": 8, 
                  "ret_data32": 4294967295, 
@@ -801,12 +856,14 @@
                  "int_lines": [
                      {
                          "name": "int_lines0", 
+                        "source": "system.pc.south_bridge.pic1.output", 
                          "eventq_index": 0, 
                          "sink": {
                              "name": "sink", 
                              "number": 0, 
                              "eventq_index": 0, 
                              "cxx_class": "X86ISA::IntSinkPin", 
+                            "device": "system.pc.south_bridge.io_apic", 
                              "path": "system.pc.south_bridge.int_lines0.sink", 
                              "type": "X86IntSinkPin"
                          }, 
@@ -816,12 +873,14 @@
                      }, 
                      {
                          "name": "int_lines1", 
+                        "source": "system.pc.south_bridge.pic2.output", 
                          "eventq_index": 0, 
                          "sink": {
                              "name": "sink", 
                              "number": 2, 
                              "eventq_index": 0, 
                              "cxx_class": "X86ISA::IntSinkPin", 
+                            "device": "system.pc.south_bridge.pic1", 
                              "path": "system.pc.south_bridge.int_lines1.sink", 
                              "type": "X86IntSinkPin"
                          }, 
@@ -831,12 +890,14 @@
                      }, 
                      {
                          "name": "int_lines2", 
+                        "source": "system.pc.south_bridge.cmos.int_pin", 
                          "eventq_index": 0, 
                          "sink": {
                              "name": "sink", 
                              "number": 0, 
                              "eventq_index": 0, 
                              "cxx_class": "X86ISA::IntSinkPin", 
+                            "device": "system.pc.south_bridge.pic2", 
                              "path": "system.pc.south_bridge.int_lines2.sink", 
                              "type": "X86IntSinkPin"
                          }, 
@@ -846,12 +907,14 @@
                      }, 
                      {
                          "name": "int_lines3", 
+                        "source": "system.pc.south_bridge.pit.int_pin", 
                          "eventq_index": 0, 
                          "sink": {
                              "name": "sink", 
                              "number": 0, 
                              "eventq_index": 0, 
                              "cxx_class": "X86ISA::IntSinkPin", 
+                            "device": "system.pc.south_bridge.pic1", 
                              "path": "system.pc.south_bridge.int_lines3.sink", 
                              "type": "X86IntSinkPin"
                          }, 
@@ -861,12 +924,14 @@
                      }, 
                      {
                          "name": "int_lines4", 
+                        "source": "system.pc.south_bridge.pit.int_pin", 
                          "eventq_index": 0, 
                          "sink": {
                              "name": "sink", 
                              "number": 2, 
                              "eventq_index": 0, 
                              "cxx_class": "X86ISA::IntSinkPin", 
+                            "device": "system.pc.south_bridge.io_apic", 
                              "path": "system.pc.south_bridge.int_lines4.sink", 
                              "type": "X86IntSinkPin"
                          }, 
@@ -876,12 +941,14 @@
                      }, 
                      {
                          "name": "int_lines5", 
+                        "source": "system.pc.south_bridge.keyboard.keyboard_int_pin", 
                          "eventq_index": 0, 
                          "sink": {
                              "name": "sink", 
                              "number": 1, 
                              "eventq_index": 0, 
                              "cxx_class": "X86ISA::IntSinkPin", 
+                            "device": "system.pc.south_bridge.io_apic", 
                              "path": "system.pc.south_bridge.int_lines5.sink", 
                              "type": "X86IntSinkPin"
                          }, 
@@ -891,12 +958,14 @@
                      }, 
                      {
                          "name": "int_lines6", 
+                        "source": "system.pc.south_bridge.keyboard.mouse_int_pin", 
                          "eventq_index": 0, 
                          "sink": {
                              "name": "sink", 
                              "number": 12, 
                              "eventq_index": 0, 
                              "cxx_class": "X86ISA::IntSinkPin", 
+                            "device": "system.pc.south_bridge.io_apic", 
                              "path": "system.pc.south_bridge.int_lines6.sink", 
                              "type": "X86IntSinkPin"
                          }, 
@@ -912,14 +981,18 @@
                          "peer": "system.iobus.master[9]", 
                          "role": "SLAVE"
                      }, 
-                    "pio_latency": 1.0000000000000001e-07, 
+                    "pio_latency": 100000, 
+                    "clk_domain": "system.clk_domain", 
+                    "system": "system", 
                      "eventq_index": 0, 
                      "cxx_class": "X86ISA::Speaker", 
                      "path": "system.pc.south_bridge.speaker", 
                      "pio_addr": 9223372036854775905, 
-                    "type": "PcSpeaker"
+                    "type": "PcSpeaker", 
+                    "i8254": "system.pc.south_bridge.pit"
                  }, 
                  "keyboard": {
+                    "system": "system", 
                      "command_port": 9223372036854775908, 
                      "name": "keyboard", 
                      "pio": {
@@ -933,7 +1006,8 @@
                          "name": "mouse_int_pin", 
                          "cxx_class": "X86ISA::IntSourcePin"
                      }, 
-                    "pio_latency": 1.0000000000000001e-07, 
+                    "pio_latency": 100000, 
+                    "clk_domain": "system.clk_domain", 
                      "keyboard_int_pin": {
                          "eventq_index": 0, 
                          "path": "system.pc.south_bridge.keyboard.keyboard_int_pin", 
@@ -954,6 +1028,7 @@
                          "peer": "system.iobus.master[8]", 
                          "role": "SLAVE"
                      }, 
+                    "pio_latency": 100000, 
                      "int_pin": {
                          "eventq_index": 0, 
                          "path": "system.pc.south_bridge.pit.int_pin", 
@@ -961,7 +1036,8 @@
                          "name": "int_pin", 
                          "cxx_class": "X86ISA::IntSourcePin"
                      }, 
-                    "pio_latency": 1.0000000000000001e-07, 
+                    "clk_domain": "system.clk_domain", 
+                    "system": "system", 
                      "eventq_index": 0, 
                      "cxx_class": "X86ISA::I8254", 
                      "path": "system.pc.south_bridge.pit", 
@@ -978,9 +1054,12 @@
                          "peer": "system.iobus.master[10]", 
                          "role": "SLAVE"
                      }, 
-                    "pio_latency": 1.0000000000000001e-07, 
+                    "pio_latency": 100000, 
+                    "clk_domain": "system.clk_domain", 
+                    "external_int_pic": "system.pc.south_bridge.pic1", 
+                    "system": "system", 
                      "apic_id": 1, 
-                    "int_latency": 1e-09, 
+                    "int_latency": 1000, 
                      "eventq_index": 0, 
                      "cxx_class": "X86ISA::I82094AA", 
                      "path": "system.pc.south_bridge.io_apic", 
@@ -988,6 +1067,7 @@
                      "type": "I82094AA"
                  }, 
                  "pic1": {
+                    "slave": "system.pc.south_bridge.pic2", 
                      "name": "pic1", 
                      "output": {
                          "eventq_index": 0, 
@@ -1000,7 +1080,9 @@
                          "peer": "system.iobus.master[6]", 
                          "role": "SLAVE"
                      }, 
-                    "pio_latency": 1.0000000000000001e-07, 
+                    "pio_latency": 100000, 
+                    "clk_domain": "system.clk_domain", 
+                    "system": "system", 
                      "eventq_index": 0, 
                      "mode": "I8259Master", 
                      "cxx_class": "X86ISA::I8259", 
@@ -1009,6 +1091,7 @@
                      "type": "I8259"
                  }, 
                  "pic2": {
+                    "slave": null, 
                      "name": "pic2", 
                      "output": {
                          "eventq_index": 0, 
@@ -1021,7 +1104,9 @@
                          "peer": "system.iobus.master[7]", 
                          "role": "SLAVE"
                      }, 
-                    "pio_latency": 1.0000000000000001e-07, 
+                    "pio_latency": 100000, 
+                    "clk_domain": "system.clk_domain", 
+                    "system": "system", 
                      "eventq_index": 0, 
                      "mode": "I8259Slave", 
                      "cxx_class": "X86ISA::I8259", 
@@ -1029,13 +1114,16 @@
                      "pio_addr": 9223372036854775968, 
                      "type": "I8259"
                  }, 
+                "platform": "system.pc", 
                  "dma1": {
                      "name": "dma1", 
                      "pio": {
                          "peer": "system.iobus.master[2]", 
                          "role": "SLAVE"
                      }, 
-                    "pio_latency": 1.0000000000000001e-07, 
+                    "pio_latency": 100000, 
+                    "clk_domain": "system.clk_domain", 
+                    "system": "system", 
                      "eventq_index": 0, 
                      "cxx_class": "X86ISA::I8237", 
                      "path": "system.pc.south_bridge.dma1", 
@@ -1054,7 +1142,9 @@
                      "MSIXCAPNextCapability": 0, 
                      "PXCAPLinkCtrl": 0, 
                      "Revision": 0, 
-                    "pio_latency": 3.0000000000000004e-08, 
+                    "LegacyIOBase": 9223372036854775808, 
+                    "pio_latency": 30000, 
+                    "platform": "system.pc", 
                      "PXCAPLinkCap": 0, 
                      "CapabilityPtr": 0, 
                      "MSIXCAPBaseOffset": 0, 
@@ -1078,21 +1168,23 @@
                              "image": {
                                  "read_only": false, 
                                  "name": "image", 
+                                "cxx_class": "CowDiskImage", 
+                                "eventq_index": 0, 
                                  "child": {
                                      "read_only": true, 
                                      "name": "child", 
                                      "eventq_index": 0, 
                                      "cxx_class": "RawDiskImage", 
                                      "path": "system.pc.south_bridge.ide.disks0.image.child", 
+                                    "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img", 
                                      "type": "RawDiskImage"
                                  }, 
-                                "eventq_index": 0, 
-                                "cxx_class": "CowDiskImage", 
                                  "path": "system.pc.south_bridge.ide.disks0.image", 
-                                "table_size": 65536, 
-                                "type": "CowDiskImage"
+                                "image_file": "", 
+                                "type": "CowDiskImage", 
+                                "table_size": 65536
                              }, 
-                            "delay": 1e-06, 
+                            "delay": 1000000, 
                              "eventq_index": 0, 
                              "cxx_class": "IdeDisk", 
                              "path": "system.pc.south_bridge.ide.disks0", 
@@ -1104,21 +1196,23 @@
                              "image": {
                                  "read_only": false, 
                                  "name": "image", 
+                                "cxx_class": "CowDiskImage", 
+                                "eventq_index": 0, 
                                  "child": {
                                      "read_only": true, 
                                      "name": "child", 
                                      "eventq_index": 0, 
                                      "cxx_class": "RawDiskImage", 
                                      "path": "system.pc.south_bridge.ide.disks1.image.child", 
+                                    "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img", 
                                      "type": "RawDiskImage"
                                  }, 
-                                "eventq_index": 0, 
-                                "cxx_class": "CowDiskImage", 
                                  "path": "system.pc.south_bridge.ide.disks1.image", 
-                                "table_size": 65536, 
-                                "type": "CowDiskImage"
+                                "image_file": "", 
+                                "type": "CowDiskImage", 
+                                "table_size": 65536
                              }, 
-                            "delay": 1e-06, 
+                            "delay": 1000000, 
                              "eventq_index": 0, 
                              "cxx_class": "IdeDisk", 
                              "path": "system.pc.south_bridge.ide.disks1", 
@@ -1157,6 +1251,7 @@
                      "MinimumGrant": 0, 
                      "Status": 640, 
                      "BAR0Size": 8, 
+                    "system": "system", 
                      "name": "ide", 
                      "PXCAPNextCapability": 0, 
                      "eventq_index": 0, 
@@ -1171,7 +1266,7 @@
                          "role": "MASTER"
                      }, 
                      "PMCAPCapId": 0, 
-                    "config_latency": 2e-08, 
+                    "config_latency": 20000, 
                      "BAR1Size": 3, 
                      "pio": {
                          "peer": "system.iobus.master[3]", 
@@ -1180,6 +1275,7 @@
                      "pci_dev": 4, 
                      "PMCAPCtrlStatus": 0, 
                      "cxx_class": "IdeController", 
+                    "clk_domain": "system.clk_domain", 
                      "SubsystemVendorID": 0, 
                      "PMCAPBaseOffset": 0, 
                      "config": {
@@ -1203,6 +1299,8 @@
                          "peer": "system.iobus.master[1]", 
                          "role": "SLAVE"
                      }, 
+                    "pio_latency": 100000, 
+                    "time": "Sun Jan  1 00:00:00 2012", 
                      "int_pin": {
                          "eventq_index": 0, 
                          "path": "system.pc.south_bridge.cmos.int_pin", 
@@ -1210,8 +1308,8 @@
                          "name": "int_pin", 
                          "cxx_class": "X86ISA::IntSourcePin"
                      }, 
-                    "time": "Sun Jan  1 00:00:00 2012", 
-                    "pio_latency": 1.0000000000000001e-07, 
+                    "clk_domain": "system.clk_domain", 
+                    "system": "system", 
                      "eventq_index": 0, 
                      "cxx_class": "X86ISA::Cmos", 
                      "path": "system.pc.south_bridge.cmos", 
@@ -1220,14 +1318,17 @@
                  }
              }, 
              "fake_floppy": {
+                "system": "system", 
                  "ret_data8": 255, 
                  "name": "fake_floppy", 
+                "warn_access": "", 
                  "pio": {
                      "peer": "system.iobus.master[17]", 
                      "role": "SLAVE"
                  }, 
                  "ret_bad_addr": false, 
-                "pio_latency": 1.0000000000000001e-07, 
+                "pio_latency": 100000, 
+                "clk_domain": "system.clk_domain", 
                  "fake_mem": false, 
                  "pio_size": 2, 
                  "ret_data32": 4294967295, 
@@ -1240,23 +1341,29 @@
                  "type": "IsaFake", 
                  "ret_data16": 65535
              }, 
+            "system": "system", 
+            "intrctrl": "system.intrctrl", 
              "com_1": {
                  "name": "com_1", 
                  "pio": {
                      "peer": "system.iobus.master[13]", 
                      "role": "SLAVE"
                  }, 
-                "pio_latency": 1.0000000000000001e-07, 
+                "pio_latency": 100000, 
+                "clk_domain": "system.clk_domain", 
+                "system": "system", 
                  "terminal": {
                      "name": "terminal", 
                      "output": true, 
                      "number": 0, 
+                    "intr_control": "system.intrctrl", 
                      "eventq_index": 0, 
                      "cxx_class": "Terminal", 
                      "path": "system.pc.com_1.terminal", 
                      "type": "Terminal", 
                      "port": 3456
                  }, 
+                "platform": "system.pc", 
                  "eventq_index": 0, 
                  "cxx_class": "Uart8250", 
                  "path": "system.pc.com_1", 
@@ -1267,14 +1374,17 @@
              "cxx_class": "Pc", 
              "path": "system.pc", 
              "behind_pci": {
+                "system": "system", 
                  "ret_data8": 255, 
                  "name": "behind_pci", 
+                "warn_access": "", 
                  "pio": {
                      "peer": "system.iobus.master[12]", 
                      "role": "SLAVE"
                  }, 
                  "ret_bad_addr": false, 
-                "pio_latency": 1.0000000000000001e-07, 
+                "pio_latency": 100000, 
+                "clk_domain": "system.clk_domain", 
                  "fake_mem": false, 
                  "pio_size": 8, 
                  "ret_data32": 4294967295, 
@@ -1289,14 +1399,17 @@
              }, 
              "type": "Pc", 
              "i_dont_exist": {
+                "system": "system", 
                  "ret_data8": 255, 
                  "name": "i_dont_exist", 
+                "warn_access": "", 
                  "pio": {
                      "peer": "system.iobus.master[11]", 
                      "role": "SLAVE"
                  }, 
                  "ret_bad_addr": false, 
-                "pio_latency": 1.0000000000000001e-07, 
+                "pio_latency": 100000, 
+                "clk_domain": "system.clk_domain", 
                  "fake_mem": false, 
                  "pio_size": 1, 
                  "ret_data32": 4294967295, 
@@ -1310,14 +1423,17 @@
                  "ret_data16": 65535
              }, 
              "fake_com_3": {
+                "system": "system", 
                  "ret_data8": 255, 
                  "name": "fake_com_3", 
+                "warn_access": "", 
                  "pio": {
                      "peer": "system.iobus.master[15]", 
                      "role": "SLAVE"
                  }, 
                  "ret_bad_addr": false, 
-                "pio_latency": 1.0000000000000001e-07, 
+                "pio_latency": 100000, 
+                "clk_domain": "system.clk_domain", 
                  "fake_mem": false, 
                  "pio_size": 8, 
                  "ret_data32": 4294967295, 
@@ -1368,71 +1484,177 @@
                      "name": "entries2"
                  }, 
                  {
-                    "addr": 4294901760, 
+                    "addr": 134217728, 
                      "range_type": 2, 
                      "eventq_index": 0, 
                      "cxx_class": "X86ISA::E820Entry", 
                      "path": "system.e820_table.entries3", 
-                    "size": 65536, 
+                    "size": 3087007744, 
                      "type": "X86E820Entry", 
                      "name": "entries3"
+                }, 
+                {
+                    "addr": 4294901760, 
+                    "range_type": 2, 
+                    "eventq_index": 0, 
+                    "cxx_class": "X86ISA::E820Entry", 
+                    "path": "system.e820_table.entries4", 
+                    "size": 65536, 
+                    "type": "X86E820Entry", 
+                    "name": "entries4"
                  }
              ], 
              "path": "system.e820_table", 
              "type": "X86E820Table"
          }, 
-        "acpi_description_table_pointer": {
-            "name": "acpi_description_table_pointer", 
-            "xsdt": {
-                "name": "xsdt", 
-                "creator_revision": 0, 
-                "eventq_index": 0, 
-                "cxx_class": "X86ISA::ACPI::XSDT", 
-                "path": "system.acpi_description_table_pointer.xsdt", 
-                "oem_revision": 0, 
-                "type": "X86ACPIXSDT"
-            }, 
+        "smbios_table": {
+            "name": "smbios_table", 
+            "structures": [
+                {
+                    "major": 0, 
+                    "vendor": "", 
+                    "name": "structures", 
+                    "characteristics": [], 
+                    "release_date": "06/08/2008", 
+                    "cxx_class": "X86ISA::SMBios::BiosInformation", 
+                    "emb_cont_firmware_major": 0, 
+                    "rom_size": 0, 
+                    "starting_addr_segment": 0, 
+                    "emb_cont_firmware_minor": 0, 
+                    "version": "", 
+                    "eventq_index": 0, 
+                    "characteristic_ext_bytes": [], 
+                    "path": "system.smbios_table.structures", 
+                    "type": "X86SMBiosBiosInformation", 
+                    "minor": 0
+                }
+            ], 
+            "major_version": 2, 
+            "minor_version": 5, 
              "eventq_index": 0, 
-            "cxx_class": "X86ISA::ACPI::RSDP", 
-            "path": "system.acpi_description_table_pointer", 
-            "type": "X86ACPIRSDP", 
-            "revision": 2
+            "cxx_class": "X86ISA::SMBios::SMBiosTable", 
+            "path": "system.smbios_table", 
+            "type": "X86SMBiosSMBiosTable"
          }, 
          "dvfs_handler": {
              "enable": false, 
              "name": "dvfs_handler", 
-            "transition_latency": 9.999999999999999e-05, 
+            "sys_clk_domain": "system.clk_domain", 
+            "transition_latency": 100000000, 
              "eventq_index": 0, 
              "cxx_class": "DVFSHandler", 
+            "domains": [], 
              "path": "system.dvfs_handler", 
              "type": "DVFSHandler"
          }, 
          "work_end_exit_count": 0, 
          "type": "LinuxX86System", 
          "voltage_domain": {
+            "name": "voltage_domain", 
              "eventq_index": 0, 
+            "voltage": [
+                "1.0"
+            ], 
+            "cxx_class": "VoltageDomain", 
              "path": "system.voltage_domain", 
-            "type": "VoltageDomain", 
-            "name": "voltage_domain", 
-            "cxx_class": "VoltageDomain"
+            "type": "VoltageDomain"
          }, 
          "cache_line_size": 64, 
-        "intel_mp_pointer": {
-            "imcr_present": true, 
-            "name": "intel_mp_pointer", 
-            "spec_rev": 4, 
-            "eventq_index": 0, 
-            "cxx_class": "X86ISA::IntelMP::FloatingPointer", 
-            "path": "system.intel_mp_pointer", 
-            "type": "X86IntelMPFloatingPointer", 
-            "default_config": 0
-        }, 
+        "boot_osflags": "earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1", 
+        "physmem": [
+            {
+                "static_frontend_latency": 10000, 
+                "tRFC": 260000, 
+                "activation_limit": 4, 
+                "in_addr_map": true, 
+                "IDD3N2": "0.0", 
+                "tWTR": 7500, 
+                "IDD52": "0.0", 
+                "clk_domain": "system.clk_domain", 
+                "channels": 1, 
+                "write_buffer_size": 64, 
+                "device_bus_width": 8, 
+                "VDD": "1.5", 
+                "write_high_thresh_perc": 85, 
+                "cxx_class": "DRAMCtrl", 
+                "bank_groups_per_rank": 0, 
+                "IDD2N2": "0.0", 
+                "port": {
+                    "peer": "system.membus.master[3]", 
+                    "role": "SLAVE"
+                }, 
+                "tCCD_L": 0, 
+                "IDD2N": "0.05", 
+                "null": false, 
+                "IDD2P1": "0.0", 
+                "eventq_index": 0, 
+                "tRRD": 6000, 
+                "tRTW": 2500, 
+                "IDD4R": "0.187", 
+                "burst_length": 8, 
+                "tRTP": 7500, 
+                "IDD4W": "0.165", 
+                "tWR": 15000, 
+                "banks_per_rank": 8, 
+                "devices_per_rank": 8, 
+                "IDD2P02": "0.0", 
+                "IDD6": "0.0", 
+                "IDD5": "0.22", 
+                "tRCD": 13750, 
+                "type": "DRAMCtrl", 
+                "IDD3P02": "0.0", 
+                "IDD0": "0.075", 
+                "IDD62": "0.0", 
+                "min_writes_per_switch": 16, 
+                "mem_sched_policy": "frfcfs", 
+                "IDD02": "0.0", 
+                "IDD2P0": "0.0", 
+                "ranks_per_channel": 2, 
+                "page_policy": "open_adaptive", 
+                "IDD4W2": "0.0", 
+                "tCS": 2500, 
+                "tCL": 13750, 
+                "read_buffer_size": 32, 
+                "conf_table_reported": true, 
+                "tCK": 1250, 
+                "tRAS": 35000, 
+                "tRP": 13750, 
+                "tBURST": 5000, 
+                "path": "system.physmem", 
+                "tXP": 0, 
+                "tXS": 0, 
+                "addr_mapping": "RoRaBaChCo", 
+                "IDD3P0": "0.0", 
+                "IDD3P1": "0.0", 
+                "IDD3N": "0.057", 
+                "name": "physmem", 
+                "tXSDLL": 0, 
+                "tXAW": 30000, 
+                "dll": true, 
+                "write_low_thresh_perc": 50, 
+                "range": "0:134217727", 
+                "VDD2": "0.0", 
+                "IDD2P12": "0.0", 
+                "tRRD_L": 0, 
+                "tXPDLL": 0, 
+                "IDD4R2": "0.0", 
+                "device_rowbuffer_size": 1024, 
+                "static_backend_latency": 10000, 
+                "max_accesses_per_row": 16, 
+                "IDD3P12": "0.0", 
+                "tREFI": 7800000
+            }
+        ], 
          "work_cpus_ckpt_count": 0, 
          "work_begin_exit_count": 0, 
          "path": "system", 
          "cpu_clk_domain": {
              "name": "cpu_clk_domain", 
+            "clock": [
+                500
+            ], 
              "init_perf_level": 0, 
+            "voltage_domain": "system.voltage_domain", 
              "eventq_index": 0, 
              "cxx_class": "SrcClockDomain", 
              "path": "system.cpu_clk_domain", 
@@ -1450,7 +1672,10 @@
                  "role": "SLAVE"
              }, 
              "name": "toL2Bus", 
+            "snoop_filter": null, 
+            "clk_domain": "system.cpu_clk_domain", 
              "header_cycles": 1, 
+            "system": "system", 
              "width": 8, 
              "eventq_index": 0, 
              "master": {
@@ -1459,51 +1684,12 @@
                  ], 
                  "role": "MASTER"
              }, 
-            "cxx_class": "CoherentBus", 
+            "cxx_class": "CoherentXBar", 
              "path": "system.toL2Bus", 
-            "type": "CoherentBus", 
+            "type": "CoherentXBar", 
              "use_default_range": false
          }, 
-        "iocache": {
-            "assoc": 8, 
-            "mem_side": {
-                "peer": "system.membus.slave[4]", 
-                "role": "MASTER"
-            }, 
-            "cpu_side": {
-                "peer": "system.iobus.master[18]", 
-                "role": "SLAVE"
-            }, 
-            "name": "iocache", 
-            "tags": {
-                "name": "tags", 
-                "eventq_index": 0, 
-                "hit_latency": 50, 
-                "sequential_access": false, 
-                "assoc": 8, 
-                "cxx_class": "LRU", 
-                "path": "system.iocache.tags", 
-                "block_size": 64, 
-                "type": "LRU", 
-                "size": 1024
-            }, 
-            "hit_latency": 50, 
-            "mshrs": 20, 
-            "response_latency": 50, 
-            "is_top_level": true, 
-            "tgts_per_mshr": 12, 
-            "sequential_access": false, 
-            "max_miss_count": 0, 
-            "eventq_index": 0, 
-            "prefetch_on_access": false, 
-            "cxx_class": "BaseCache", 
-            "path": "system.iocache", 
-            "write_buffers": 8, 
-            "two_queue": false, 
-            "type": "BaseCache", 
-            "forward_snoops": false, 
-            "size": 1024
-        }, 
+        "work_end_ckpt_count": 0, 
          "mem_mode": "atomic", 
          "name": "system", 
          "init_param": 0, 
@@ -1514,7 +1700,6 @@
          "load_addr_mask": 18446744073709551615, 
          "cpu": [
              {
-                "simpoint_interval": 100000000, 
                  "do_statistics_insts": true, 
                  "numThreads": 1, 
                  "itb": {
@@ -1523,6 +1708,8 @@
                      "cxx_class": "X86ISA::TLB", 
                      "walker": {
                          "name": "walker", 
+                        "clk_domain": "system.cpu_clk_domain", 
+                        "system": "system", 
                          "eventq_index": 0, 
                          "cxx_class": "X86ISA::Walker", 
                          "path": "system.cpu0.itb.walker", 
@@ -1537,47 +1724,48 @@
                      "type": "X86TLB", 
                      "size": 64
                  }, 
+                "simulate_data_stalls": false, 
                  "function_trace": false, 
                  "do_checkpoint_insts": true, 
                  "cxx_class": "AtomicSimpleCPU", 
                  "max_loads_all_threads": 0, 
+                "system": "system", 
                  "apic_clk_domain": {
                      "name": "apic_clk_domain", 
+                    "clk_domain": "system.cpu_clk_domain", 
                      "eventq_index": 0, 
                      "cxx_class": "DerivedClockDomain", 
                      "path": "system.cpu0.apic_clk_domain", 
                      "type": "DerivedClockDomain", 
                      "clk_divider": 16
                  }, 
-                "simpoint_profile": false, 
-                "simulate_data_stalls": false, 
+                "clk_domain": "system.cpu_clk_domain", 
                  "function_trace_start": 0, 
                  "cpu_id": 0, 
                  "width": 1, 
+                "checker": null, 
                  "eventq_index": 0, 
                  "do_quiesce": true, 
                  "type": "AtomicSimpleCPU", 
                  "fastmem": false, 
-                "profile": 0.0, 
+                "profile": 0, 
                  "icache_port": {
                      "peer": "system.cpu0.icache.cpu_side", 
                      "role": "MASTER"
                  }, 
                  "icache": {
-                    "assoc": 1, 
-                    "mem_side": {
-                        "peer": "system.toL2Bus.slave[0]", 
-                        "role": "MASTER"
-                    }, 
-                    "cpu_side": {
-                        "peer": "system.cpu0.icache_port", 
-                        "role": "SLAVE"
-                    }, 
-                    "name": "icache", 
+                    "is_top_level": true, 
+                    "prefetcher": null, 
+                    "clk_domain": "system.cpu_clk_domain", 
+                    "write_buffers": 8, 
+                    "response_latency": 2, 
+                    "cxx_class": "BaseCache", 
+                    "size": 32768, 
                      "tags": {
                          "name": "tags", 
                          "eventq_index": 0, 
                          "hit_latency": 2, 
+                        "clk_domain": "system.cpu_clk_domain", 
                          "sequential_access": false, 
                          "assoc": 1, 
                          "cxx_class": "LRU", 
@@ -1586,22 +1774,31 @@
                          "type": "LRU", 
                          "size": 32768
                      }, 
-                    "hit_latency": 2, 
-                    "mshrs": 4, 
-                    "response_latency": 2, 
-                    "is_top_level": true, 
-                    "tgts_per_mshr": 20, 
-                    "sequential_access": false, 
+                    "system": "system", 
                      "max_miss_count": 0, 
                      "eventq_index": 0, 
+                    "mem_side": {
+                        "peer": "system.toL2Bus.slave[0]", 
+                        "role": "MASTER"
+                    }, 
+                    "mshrs": 4, 
+                    "forward_snoops": true, 
+                    "hit_latency": 2, 
+                    "tgts_per_mshr": 20, 
+                    "addr_ranges": [
+                        "0:18446744073709551615"
+                    ], 
+                    "assoc": 1, 
                      "prefetch_on_access": false, 
-                    "cxx_class": "BaseCache", 
                      "path": "system.cpu0.icache", 
-                    "write_buffers": 8, 
-                    "two_queue": false, 
+                    "name": "icache", 
                      "type": "BaseCache", 
-                    "forward_snoops": true, 
-                    "size": 32768
+                    "sequential_access": false, 
+                    "cpu_side": {
+                        "peer": "system.cpu0.icache_port", 
+                        "role": "SLAVE"
+                    }, 
+                    "two_queue": false
                  }, 
                  "interrupts": {
                      "int_master": {
@@ -1613,31 +1810,30 @@
                          "peer": "system.membus.master[1]", 
                          "role": "SLAVE"
                      }, 
-                    "pio_latency": 1.0000000000000001e-07, 
                      "int_slave": {
                          "peer": "system.membus.master[2]", 
                          "role": "SLAVE"
                      }, 
-                    "int_latency": 1e-09, 
+                    "pio_latency": 100000, 
+                    "clk_domain": "system.cpu0.apic_clk_domain", 
+                    "system": "system", 
+                    "int_latency": 1000, 
                      "eventq_index": 0, 
                      "cxx_class": "X86ISA::Interrupts", 
                      "path": "system.cpu0.interrupts", 
                      "pio_addr": 2305843009213693952, 
                      "type": "X86LocalApic"
                  }, 
+                "dcache_port": {
+                    "peer": "system.cpu0.dcache.cpu_side", 
+                    "role": "MASTER"
+                }, 
                  "socket_id": 0, 
                  "max_insts_all_threads": 0, 
                  "path": "system.cpu0", 
-                "isa": [
-                    {
-                        "eventq_index": 0, 
-                        "path": "system.cpu0.isa", 
-                        "type": "X86ISA", 
-                        "name": "isa", 
-                        "cxx_class": "X86ISA::ISA"
-                    }
-                ], 
+                "max_loads_any_thread": 0, 
                  "switched_out": false, 
+                "workload": [], 
                  "name": "cpu0", 
                  "dtb": {
                      "name": "dtb", 
@@ -1645,6 +1841,8 @@
                      "cxx_class": "X86ISA::TLB", 
                      "walker": {
                          "name": "walker", 
+                        "clk_domain": "system.cpu_clk_domain", 
+                        "system": "system", 
                          "eventq_index": 0, 
                          "cxx_class": "X86ISA::Walker", 
                          "path": "system.cpu0.dtb.walker", 
@@ -1659,28 +1857,24 @@
                      "type": "X86TLB", 
                      "size": 64
                  }, 
+                "simpoint_start_insts": [], 
                  "max_insts_any_thread": 0, 
                  "simulate_inst_stalls": false, 
-                "progress_interval": 0.0, 
-                "dcache_port": {
-                    "peer": "system.cpu0.dcache.cpu_side", 
-                    "role": "MASTER"
-                }, 
+                "progress_interval": 0, 
+                "branchPred": null, 
                  "dcache": {
-                    "assoc": 4, 
-                    "mem_side": {
-                        "peer": "system.toL2Bus.slave[1]", 
-                        "role": "MASTER"
-                    }, 
-                    "cpu_side": {
-                        "peer": "system.cpu0.dcache_port", 
-                        "role": "SLAVE"
-                    }, 
-                    "name": "dcache", 
+                    "is_top_level": true, 
+                    "prefetcher": null, 
+                    "clk_domain": "system.cpu_clk_domain", 
+                    "write_buffers": 8, 
+                    "response_latency": 2, 
+                    "cxx_class": "BaseCache", 
+                    "size": 32768, 
                      "tags": {
                          "name": "tags", 
                          "eventq_index": 0, 
                          "hit_latency": 2, 
+                        "clk_domain": "system.cpu_clk_domain", 
                          "sequential_access": false, 
                          "assoc": 4, 
                          "cxx_class": "LRU", 
@@ -1689,24 +1883,41 @@
                          "type": "LRU", 
                          "size": 32768
                      }, 
-                    "hit_latency": 2, 
-                    "mshrs": 4, 
-                    "response_latency": 2, 
-                    "is_top_level": true, 
-                    "tgts_per_mshr": 20, 
-                    "sequential_access": false, 
+                    "system": "system", 
                      "max_miss_count": 0, 
                      "eventq_index": 0, 
+                    "mem_side": {
+                        "peer": "system.toL2Bus.slave[1]", 
+                        "role": "MASTER"
+                    }, 
+                    "mshrs": 4, 
+                    "forward_snoops": true, 
+                    "hit_latency": 2, 
+                    "tgts_per_mshr": 20, 
+                    "addr_ranges": [
+                        "0:18446744073709551615"
+                    ], 
+                    "assoc": 4, 
                      "prefetch_on_access": false, 
-                    "cxx_class": "BaseCache", 
                      "path": "system.cpu0.dcache", 
-                    "write_buffers": 8, 
-                    "two_queue": false, 
+                    "name": "dcache", 
                      "type": "BaseCache", 
-                    "forward_snoops": true, 
-                    "size": 32768
+                    "sequential_access": false, 
+                    "cpu_side": {
+                        "peer": "system.cpu0.dcache_port", 
+                        "role": "SLAVE"
+                    }, 
+                    "two_queue": false
                  }, 
-                "max_loads_any_thread": 0, 
+                "isa": [
+                    {
+                        "eventq_index": 0, 
+                        "path": "system.cpu0.isa", 
+                        "type": "X86ISA", 
+                        "name": "isa", 
+                        "cxx_class": "X86ISA::ISA"
+                    }
+                ], 
                  "tracer": {
                      "eventq_index": 0, 
                      "path": "system.cpu0.tracer", 
@@ -1724,6 +1935,8 @@
                      "cxx_class": "X86ISA::TLB", 
                      "walker": {
                          "name": "walker", 
+                        "clk_domain": "system.cpu_clk_domain", 
+                        "system": "system", 
                          "eventq_index": 0, 
                          "cxx_class": "X86ISA::Walker", 
                          "path": "system.cpu1.itb.walker", 
@@ -1734,29 +1947,26 @@
                      "type": "X86TLB", 
                      "size": 64
                  }, 
+                "system": "system", 
                  "function_trace": false, 
                  "do_checkpoint_insts": true, 
                  "cxx_class": "TimingSimpleCPU", 
                  "max_loads_all_threads": 0, 
+                "clk_domain": "system.cpu_clk_domain", 
                  "function_trace_start": 0, 
                  "cpu_id": 0, 
+                "checker": null, 
                  "eventq_index": 0, 
                  "do_quiesce": true, 
                  "type": "TimingSimpleCPU", 
-                "profile": 0.0, 
+                "profile": 0, 
+                "interrupts": null, 
                  "socket_id": 0, 
                  "max_insts_all_threads": 0, 
                  "path": "system.cpu1", 
-                "isa": [
-                    {
-                        "eventq_index": 0, 
-                        "path": "system.cpu1.isa", 
-                        "type": "X86ISA", 
-                        "name": "isa", 
-                        "cxx_class": "X86ISA::ISA"
-                    }
-                ], 
+                "max_loads_any_thread": 0, 
                  "switched_out": true, 
+                "workload": [], 
                  "name": "cpu1", 
                  "dtb": {
                      "name": "dtb", 
@@ -1764,6 +1974,8 @@
                      "cxx_class": "X86ISA::TLB", 
                      "walker": {
                          "name": "walker", 
+                        "clk_domain": "system.cpu_clk_domain", 
+                        "system": "system", 
                          "eventq_index": 0, 
                          "cxx_class": "X86ISA::Walker", 
                          "path": "system.cpu1.dtb.walker", 
@@ -1774,9 +1986,19 @@
                      "type": "X86TLB", 
                      "size": 64
                  }, 
+                "simpoint_start_insts": [], 
                  "max_insts_any_thread": 0, 
-                "progress_interval": 0.0, 
-                "max_loads_any_thread": 0, 
+                "progress_interval": 0, 
+                "branchPred": null, 
+                "isa": [
+                    {
+                        "eventq_index": 0, 
+                        "path": "system.cpu1.isa", 
+                        "type": "X86ISA", 
+                        "name": "isa", 
+                        "cxx_class": "X86ISA::ISA"
+                    }
+                ], 
                  "tracer": {
                      "eventq_index": 0, 
                      "path": "system.cpu1.tracer", 
@@ -1788,8 +2010,7 @@
              {
                  "SQEntries": 32, 
                  "smtLSQThreshold": 100, 
-                "do_statistics_insts": true, 
-                "dispatchWidth": 8, 
+                "fetchTrapLatency": 1, 
                  "iewToRenameDelay": 1, 
                  "itb": {
                      "name": "itb", 
@@ -1797,6 +2018,8 @@
                      "cxx_class": "X86ISA::TLB", 
                      "walker": {
                          "name": "walker", 
+                        "clk_domain": "system.cpu_clk_domain", 
+                        "system": "system", 
                          "eventq_index": 0, 
                          "cxx_class": "X86ISA::Walker", 
                          "path": "system.cpu2.itb.walker", 
@@ -1807,26 +2030,39 @@
                      "type": "X86TLB", 
                      "size": 64
                  }, 
-                "wbWidth": 8, 
-                "squashWidth": 8, 
-                "forwardComSize": 5, 
-                "function_trace": false, 
-                "do_checkpoint_insts": true, 
                  "fetchWidth": 8, 
-                "cxx_class": "DerivO3CPU", 
-                "backComSize": 5, 
-                "switched_out": true, 
                  "max_loads_all_threads": 0, 
-                "numROBEntries": 192, 
-                "commitToIEWDelay": 1, 
-                "commitToDecodeDelay": 1, 
-                "decodeToRenameDelay": 1, 
+                "cpu_id": 0, 
                  "fetchToDecodeDelay": 1, 
-                "issueWidth": 8, 
-                "LSQCheckLoads": true, 
-                "commitToRenameDelay": 1, 
                  "renameToDecodeDelay": 1, 
-                "wbDepth": 1, 
+                "do_quiesce": true, 
+                "renameToROBDelay": 1, 
+                "max_insts_all_threads": 0, 
+                "decodeWidth": 8, 
+                "commitToFetchDelay": 1, 
+                "needsTSO": true, 
+                "smtIQThreshold": 100, 
+                "workload": [], 
+                "name": "cpu2", 
+                "SSITSize": 1024, 
+                "activity": 0, 
+                "max_loads_any_thread": 0, 
+                "tracer": {
+                    "eventq_index": 0, 
+                    "path": "system.cpu2.tracer", 
+                    "type": "ExeTracer", 
+                    "name": "tracer", 
+                    "cxx_class": "Trace::ExeTracer"
+                }, 
+                "decodeToFetchDelay": 1, 
+                "renameWidth": 8, 
+                "numThreads": 1, 
+                "squashWidth": 8, 
+                "function_trace": false, 
+                "backComSize": 5, 
+                "decodeToRenameDelay": 1, 
+                "store_set_clear_period": 250000, 
+                "numPhysIntRegs": 256, 
                  "fuPool": {
                      "name": "fuPool", 
                      "FUList": [
@@ -2266,33 +2502,17 @@
                      "path": "system.cpu2.fuPool", 
                      "type": "FUPool"
                  }, 
-                "cachePorts": 200, 
-                "function_trace_start": 0, 
-                "cpu_id": 0, 
-                "store_set_clear_period": 250000, 
-                "numPhysFloatRegs": 256, 
-                "eventq_index": 0, 
-                "smtNumFetchingThreads": 1, 
-                "numThreads": 1, 
-                "numPhysIntRegs": 256, 
-                "do_quiesce": true, 
-                "type": "DerivO3CPU", 
-                "isa": [
-                    {
-                        "eventq_index": 0, 
-                        "path": "system.cpu2.isa", 
-                        "type": "X86ISA", 
-                        "name": "isa", 
-                        "cxx_class": "X86ISA::ISA"
-                    }
-                ], 
+                "socket_id": 0, 
+                "renameToFetchDelay": 1, 
+                "path": "system.cpu2", 
+                "numRobs": 1, 
+                "switched_out": true, 
+                "smtLSQPolicy": "Partitioned", 
+                "fetchBufferSize": 64, 
+                "simpoint_start_insts": [], 
+                "max_insts_any_thread": 0, 
                  "smtROBThreshold": 100, 
-                "profile": 0.0, 
-                "renameToROBDelay": 1, 
-                "commitToFetchDelay": 1, 
-                "fetchTrapLatency": 1, 
-                "progress_interval": 0.0, 
-                "commitWidth": 8, 
+                "numIQEntries": 64, 
                  "branchPred": {
                      "choiceCtrBits": 2, 
                      "name": "branchPred", 
@@ -2309,32 +2529,47 @@
                      "path": "system.cpu2.branchPred", 
                      "localPredictorSize": 2048, 
                      "type": "BranchPredictor", 
+                    "predType": "tournament", 
                      "RASSize": 16, 
                      "globalPredictorSize": 8192
                  }, 
-                "socket_id": 0, 
-                "numPhysCCRegs": 1280, 
-                "renameToFetchDelay": 1, 
-                "LSQDepCheckShift": 4, 
-                "decodeWidth": 8, 
-                "trapLatency": 13, 
-                "needsTSO": true, 
-                "renameWidth": 8, 
-                "path": "system.cpu2", 
-                "max_insts_all_threads": 0, 
-                "max_loads_any_thread": 0, 
-                "numRobs": 1, 
-                "iewToDecodeDelay": 1, 
-                "max_insts_any_thread": 0, 
+                "LFSTSize": 1024, 
+                "isa": [
+                    {
+                        "eventq_index": 0, 
+                        "path": "system.cpu2.isa", 
+                        "type": "X86ISA", 
+                        "name": "isa", 
+                        "cxx_class": "X86ISA::ISA"
+                    }
+                ], 
+                "smtROBPolicy": "Partitioned", 
+                "iewToFetchDelay": 1, 
+                "do_statistics_insts": true, 
+                "dispatchWidth": 8, 
+                "commitToDecodeDelay": 1, 
+                "smtIQPolicy": "Partitioned", 
+                "issueWidth": 8, 
+                "LSQCheckLoads": true, 
+                "commitToRenameDelay": 1, 
+                "cachePorts": 200, 
+                "system": "system", 
+                "checker": null, 
+                "numPhysFloatRegs": 256, 
+                "eventq_index": 0, 
+                "type": "DerivO3CPU", 
+                "wbWidth": 8, 
+                "interrupts": null, 
+                "smtCommitPolicy": "RoundRobin", 
                  "issueToExecuteDelay": 1, 
-                "name": "cpu2", 
-                "fetchBufferSize": 64, 
                  "dtb": {
                      "name": "dtb", 
                      "eventq_index": 0, 
                      "cxx_class": "X86ISA::TLB", 
                      "walker": {
                          "name": "walker", 
+                        "clk_domain": "system.cpu_clk_domain", 
+                        "system": "system", 
                          "eventq_index": 0, 
                          "cxx_class": "X86ISA::Walker", 
                          "path": "system.cpu2.dtb.walker", 
@@ -2345,39 +2580,44 @@
                      "type": "X86TLB", 
                      "size": 64
                  }, 
-                "SSITSize": 1024, 
-                "LQEntries": 32, 
-                "numIQEntries": 64, 
-                "activity": 0, 
-                "LFSTSize": 1024, 
+                "numROBEntries": 192, 
+                "fetchQueueSize": 32, 
                  "iewToCommitDelay": 1, 
+                "smtNumFetchingThreads": 1, 
+                "forwardComSize": 5, 
+                "do_checkpoint_insts": true, 
+                "cxx_class": "DerivO3CPU", 
+                "commitToIEWDelay": 1, 
+                "commitWidth": 8, 
+                "clk_domain": "system.cpu_clk_domain", 
+                "function_trace_start": 0, 
+                "smtFetchPolicy": "SingleThread", 
+                "profile": 0, 
+                "LSQDepCheckShift": 4, 
+                "trapLatency": 13, 
+                "iewToDecodeDelay": 1, 
+                "numPhysCCRegs": 1280, 
                  "renameToIEWDelay": 2, 
-                "iewToFetchDelay": 1, 
-                "tracer": {
-                    "eventq_index": 0, 
-                    "path": "system.cpu2.tracer", 
-                    "type": "ExeTracer", 
-                    "name": "tracer", 
-                    "cxx_class": "Trace::ExeTracer"
-                }, 
-                "decodeToFetchDelay": 1, 
-                "smtIQThreshold": 100
+                "progress_interval": 0, 
+                "LQEntries": 32
              }
          ], 
          "intrctrl": {
+            "name": "intrctrl", 
+            "sys": "system", 
              "eventq_index": 0, 
+            "cxx_class": "IntrControl", 
              "path": "system.intrctrl", 
-            "type": "IntrControl", 
-            "name": "intrctrl", 
-            "cxx_class": "IntrControl"
+            "type": "IntrControl"
          }, 
-        "num_work_ids": 16, 
+        "work_begin_ckpt_count": 0, 
+        "work_begin_cpu_id_exit": -1, 
          "work_item_id": -1, 
-        "work_begin_cpu_id_exit": -1
+        "num_work_ids": 16
      }, 
-    "time_sync_period": 0.1, 
+    "time_sync_period": 100000000000, 
      "eventq_index": 0, 
-    "time_sync_spin_threshold": 9.999999999999999e-05, 
+    "time_sync_spin_threshold": 100000000, 
      "cxx_class": "Root", 
      "path": "root", 
      "time_sync_enable": false, 
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

index 9fd6d97ff4a01d6539933098825b70d07b129f92..e53b3f28544afdcf4009fc8cc715ea888ea4142c 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,150 +1,154 @@
  
  ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.133872                       # Number of seconds simulated
-sim_ticks                                5133872107500                       # Number of ticks simulated
-final_tick                               5133872107500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.137752                       # Number of seconds simulated
+sim_ticks                                5137751757500                       # Number of ticks simulated
+final_tick                               5137751757500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
  sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 332026                       # Simulator instruction rate (inst/s)
-host_op_rate                                   659988                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6979227984                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 973372                       # Number of bytes of host memory used
-host_seconds                                   735.59                       # Real time elapsed on the host
-sim_insts                                   244235751                       # Number of instructions simulated
-sim_ops                                     485482573                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 205879                       # Simulator instruction rate (inst/s)
+host_op_rate                                   409313                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4343855741                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 976756                       # Number of bytes of host memory used
+host_seconds                                  1182.76                       # Real time elapsed on the host
+sim_insts                                   243506025                       # Number of instructions simulated
+sim_ops                                     484120527                       # Number of ops (including micro ops) simulated
  system.voltage_domain.voltage                       1                       # Voltage in Volts
  system.clk_domain.clock                          1000                       # Clock period in ticks
  system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           396736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5572928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           164928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1639680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         2240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           412864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          3220800                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11438848                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       396736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       164928                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       412864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          974528                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6205312                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           475328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5564736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           130048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2113344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         2688                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           362880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2752000                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11429696                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       475328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       130048                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       362880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          968256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6180416                       # Number of bytes written to this memory
  system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9195392                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9170496                       # Number of bytes written to this memory
  system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6199                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             87077                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2577                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             25620                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           35                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              6451                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             50325                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                178732                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           96958                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              7427                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             86949                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2032                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             33021                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           42                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5670                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             43000                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                178589                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           96569                       # Number of write requests responded to by this memory
  system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143678                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide         5523                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               77278                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1085521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               32125                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              319385                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           436                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               80420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              627363                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2228113                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          77278                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          32125                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          80420                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             189823                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1208700                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       582422                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1791122                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1208700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       587945                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              77278                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1085521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              32125                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             319385                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          436                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              80420                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             627363                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4019235                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         85451                       # Number of read requests accepted
-system.physmem.writeReqs                        85019                       # Number of write requests accepted
-system.physmem.readBursts                       85451                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      85019                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5457024                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11840                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5440128                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5468864                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5441216                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      185                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total               143289                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         5518                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               92517                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1083107                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               25312                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              411336                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           523                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               70630                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              535643                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2224649                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          92517                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          25312                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          70630                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             188459                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1202942                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       581982                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1784924                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1202942                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       587501                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              92517                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1083107                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              25312                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             411336                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          523                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              70630                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             535643                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4009573                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         84209                       # Number of read requests accepted
+system.physmem.writeReqs                        74716                       # Number of write requests accepted
+system.physmem.readBursts                       84209                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      74716                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5376960                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     12416                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4781824                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5389376                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4781824                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      194                       # Number of DRAM read bursts serviced by the write queue
  system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            868                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5096                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                5035                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5503                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5713                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5011                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                4756                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                4921                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5413                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5128                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                4999                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               4701                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5348                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5396                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6167                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6376                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5703                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5743                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5870                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5006                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5323                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4689                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4481                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5327                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5300                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5281                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5131                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5421                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5658                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               5171                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5597                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5966                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5038                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            805                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5309                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                4164                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                4421                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5747                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5625                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                4848                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                4889                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                4803                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5153                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                5288                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               4847                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5280                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5573                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6540                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6055                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5473                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4689                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                3818                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                3922                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4862                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4936                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4229                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4848                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4482                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4577                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4853                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4451                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               4689                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4903                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               5464                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5149                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4844                       # Per bank write bursts
  system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
  system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5132871981000                       # Total gap between requests
+system.physmem.totGap                    5136577016500                       # Total gap between requests
  system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   85451                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   84209                       # Read request sizes (log2)
  system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  85019                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     78990                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4833                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       949                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        40                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  74716                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     79815                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      3315                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       428                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        41                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       26                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
@@ -164,487 +168,497 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
  system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5006                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5996                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4932                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1661                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3664                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3881                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4751                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5087                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5589                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4864                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4484                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4396                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     3849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     3706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     3707                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     3671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
  system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        39962                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      272.686252                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     163.690614                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     301.316153                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          16345     40.90%     40.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9834     24.61%     65.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4112     10.29%     75.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2230      5.58%     81.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1552      3.88%     85.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1069      2.68%     87.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          711      1.78%     89.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          597      1.49%     91.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3512      8.79%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          39962                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4105                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.770767                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      117.592245                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255            4095     99.76%     99.76% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511             7      0.17%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767             1      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-2815            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6656-6911            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4105                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4105                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.706943                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.214534                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.616872                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                63      1.53%      1.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 7      0.17%      1.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                1      0.02%      1.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               4      0.10%      1.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            3359     81.83%     83.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              49      1.19%     84.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              26      0.63%     85.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             173      4.21%     89.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             182      4.43%     94.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               7      0.17%     94.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              12      0.29%     94.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               8      0.19%     94.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              10      0.24%     95.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               2      0.05%     95.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.02%     95.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               1      0.02%     95.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             157      3.82%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.02%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               3      0.07%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              10      0.24%     99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               7      0.17%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.05%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.05%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             5      0.12%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.05%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.19%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4105                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1041221500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2639959000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    426330000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12211.45                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples        37237                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      272.814244                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     163.615678                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     301.614315                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15278     41.03%     41.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9118     24.49%     65.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3769     10.12%     75.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2135      5.73%     81.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1492      4.01%     85.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          936      2.51%     87.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          657      1.76%     89.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          562      1.51%     91.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3290      8.84%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          37237                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3726                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.548309                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      194.901220                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            3723     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            1      0.03%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5632-6143            1      0.03%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9728-10239            1      0.03%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            3726                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3726                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.052603                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.849959                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.299765                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                61      1.64%      1.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 9      0.24%      1.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                1      0.03%      1.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               4      0.11%      2.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            3105     83.33%     85.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              37      0.99%     86.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              24      0.64%     86.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             154      4.13%     91.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             145      3.89%     95.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               6      0.16%     95.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              11      0.30%     95.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               2      0.05%     95.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              14      0.38%     95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               4      0.11%     96.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.03%     96.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             119      3.19%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.13%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               1      0.03%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               1      0.03%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.16%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               4      0.11%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.03%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.03%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             9      0.24%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3726                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      920887750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2496169000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    420075000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10960.99                       # Average queueing delay per DRAM burst
  system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30961.45                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.06                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.06                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.07                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.06                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29710.99                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.05                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.93                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.05                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.93                       # Average system write bandwidth in MiByte/s
  system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
  system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
  system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
  system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
  system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         6.94                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      67077                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     63228                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   78.67                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.37                       # Row buffer hit rate for writes
-system.physmem.avgGap                     30110118.97                       # Average gap between requests
-system.physmem.pageHitRate                      76.52                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4938526642750                       # Time in different power states
-system.physmem.memoryStateTime::REF      171431260000                       # Time in different power states
+system.physmem.avgWrQLen                        12.74                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      66918                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     54576                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   79.65                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.04                       # Row buffer hit rate for writes
+system.physmem.avgGap                     32320761.47                       # Average gap between requests
+system.physmem.pageHitRate                      76.54                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4942660463000                       # Time in different power states
+system.physmem.memoryStateTime::REF      171560740000                       # Time in different power states
  system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       23914099250                       # Time in different power states
+system.physmem.memoryStateTime::ACT       23528333250                       # Time in different power states
  system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 145575360                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 156537360                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                  79431000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                  85412250                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                323294400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                341772600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               270468720                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               280344240                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          335319544560                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          335319544560                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          122941148535                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          123404461065                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          2972480080500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          2972073666000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            3431559543075                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            3431661738075                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.415487                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.435393                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq             5056260                       # Transaction distribution
-system.membus.trans_dist::ReadResp            5056258                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13754                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13754                       # Transaction distribution
-system.membus.trans_dist::Writeback             96958                       # Transaction distribution
+system.physmem.actEnergy::0                 135618840                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 145892880                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                  73998375                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                  79604250                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                310486800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                344830200                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               231893280                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               252266400                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          335572807440                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          335572807440                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          122729524065                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          123386936985                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          2974992236250                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          2974415558250                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            3434046565050                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            3434197896405                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.395092                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.424547                       # Core power per rank (mW)
+system.membus.trans_dist::ReadReq             5119571                       # Transaction distribution
+system.membus.trans_dist::ReadResp            5119569                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13900                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13900                       # Transaction distribution
+system.membus.trans_dist::Writeback             96569                       # Transaction distribution
  system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
  system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             1654                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1654                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129924                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129924                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1664                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1664                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             1658                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1658                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130179                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130179                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1687                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1687                       # Transaction distribution
  system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3328                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3328                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7028524                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3012958                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       456844                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3374                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3374                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7129206                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3039990                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       456177                       # Packet count per connected master and slave (bytes)
  system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total     10498330                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94955                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        94955                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               10596613                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3520458                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6025913                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17615808                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     27162179                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3029056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      3029056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                30197891                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              297                       # Total snoops (count)
-system.membus.snoop_fanout::samples            324529                       # Request fanout histogram
+system.membus.pkt_count_system.l2c.mem_side::total     10625377                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94957                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        94957                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               10723708                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6748                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6748                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3570760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6079977                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17581760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     27232497                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3029312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      3029312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                30268557                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              291                       # Total snoops (count)
+system.membus.snoop_fanout::samples            323999                       # Request fanout histogram
  system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
  system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
  system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
  system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  324529    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  323999    100.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
  system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              324529                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           165183000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              323999                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           162958500                       # Layer occupancy (ticks)
  system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           315920500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           314938500                       # Layer occupancy (ticks)
  system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1960000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             2254000                       # Layer occupancy (ticks)
  system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           897247500                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           804193000                       # Layer occupancy (ticks)
  system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                2000                       # Layer occupancy (ticks)
  system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy             980000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1127000                       # Layer occupancy (ticks)
  system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1679098885                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1664243698                       # Layer occupancy (ticks)
  system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           35042997                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           28678745                       # Layer occupancy (ticks)
  system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
  system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   105529                       # number of replacements
-system.l2c.tags.tagsinuse                64826.632454                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3692969                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169653                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.767779                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   104648                       # number of replacements
+system.l2c.tags.tagsinuse                64825.327064                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3691316                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   168821                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.865266                       # Average number of references to valid blocks.
  system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   50921.041202                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134275                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1022.158767                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3887.538850                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      285.540185                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1563.161522                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    13.370475                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1774.545144                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     5359.142034                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.776993                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   51329.060133                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.131449                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1735.761730                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4946.132925                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.003182                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      379.214744                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1982.386911                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    11.162749                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst      878.696468                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     3562.776774                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.783219                       # Average percentage of cache occupancy
  system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.015597                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.059319                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.004357                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.023852                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000204                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.027077                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.081774                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.989176                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64124                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          541                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3271                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7391                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52860                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.978455                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 33891981                       # Number of tag accesses
-system.l2c.tags.data_accesses                33891981                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        19672                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        10574                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             322011                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             496358                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        11305                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         6290                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             162787                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             241655                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        55032                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        13181                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             370296                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             572247                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2281408                       # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst       0.026486                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.075472                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.005786                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.030249                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000170                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.013408                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.054364                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.989156                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        64173                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3770                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7642                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52446                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.979202                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 33857298                       # Number of tag accesses
+system.l2c.tags.data_accesses                33857298                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        21885                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker        11413                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             321088                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             497388                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        12632                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         6595                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             160077                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             224317                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        53710                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker        12539                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             370609                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             592462                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2284715                       # number of ReadReq hits
  system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
  system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks         1548978                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1548978                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             124                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              47                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              90                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 261                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            66428                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            37696                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            62332                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               166456                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         19672                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         10576                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              322011                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              562786                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         11305                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          6290                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              162787                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              279351                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         55032                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         13181                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              370296                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              634579                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2447866                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        19672                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        10576                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             322011                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             562786                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        11305                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         6290                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             162787                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             279351                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        55032                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        13181                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             370296                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             634579                       # number of overall hits
-system.l2c.overall_hits::total                2447866                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             6199                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data            12693                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             2577                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             4439                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker           35                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst             6453                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data            15968                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                48369                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data           700                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           296                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           406                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1402                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          74470                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          21268                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          34438                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             130176                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              6199                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             87163                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2577                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             25707                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker           35                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              6453                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             50406                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                178545                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             6199                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            87163                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2577                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            25707                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker           35                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             6453                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            50406                       # number of overall misses
-system.l2c.overall_misses::total               178545                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst    188438000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    344143000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      2792750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst    504402750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data   1264657500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     2304434000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      3069868                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data      4534805                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      7604673                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1465791412                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   2496772674                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   3962564086                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    188438000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1809934412                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker      2792750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    504402750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   3761430174                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      6266998086                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    188438000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1809934412                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker      2792750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    504402750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   3761430174                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     6266998086                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        19672                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker        10579                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         328210                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         509051                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        11305                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         6290                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         165364                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         246094                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker        55067                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker        13181                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst         376749                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data         588215                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2329777                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_hits::writebacks         1547592                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1547592                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             126                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              49                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data              89                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 264                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            63533                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            34910                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            62567                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               161010                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         21885                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker         11415                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              321088                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              560921                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         12632                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          6595                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              160077                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              259227                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker         53710                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker         12539                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              370609                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              655029                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2445727                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        21885                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker        11415                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             321088                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             560921                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        12632                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         6595                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             160077                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             259227                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker        53710                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker        12539                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             370609                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             655029                       # number of overall hits
+system.l2c.overall_hits::total                2445727                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             7427                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data            17501                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             2032                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             4808                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker           42                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst             5670                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data            10484                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                47969                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data           766                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           250                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data           384                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1400                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          69535                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          28299                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          32603                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             130437                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              7427                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             87036                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2032                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             33107                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker           42                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              5670                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             43087                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                178406                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.itb.walker            4                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             7427                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            87036                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2032                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            33107                       # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker           42                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             5670                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            43087                       # number of overall misses
+system.l2c.overall_misses::total               178406                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker        74500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    150329750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    367685500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      3647250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst    442043250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data    814497000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1778277250                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      2652136                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data      4441809                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      7093945                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1942003664                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   2343046915                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   4285050579                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker        74500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    150329750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   2309689164                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker      3647250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    442043250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   3157543915                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      6063327829                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker        74500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    150329750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   2309689164                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker      3647250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    442043250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   3157543915                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     6063327829                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        21885                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker        11417                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         328515                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         514889                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        12632                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         6596                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         162109                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         229125                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker        53752                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker        12539                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst         376279                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data         602946                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2332684                       # number of ReadReq accesses(hits+misses)
  system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
  system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1548978                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1548978                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data          824                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          343                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data          496                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1663                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       140898                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        58964                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        96770                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           296632                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        19672                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker        10581                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          328210                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          649949                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        11305                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6290                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          165364                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          305058                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker        55067                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker        13181                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          376749                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          684985                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2626411                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        19672                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker        10581                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         328210                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         649949                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        11305                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6290                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         165364                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         305058                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker        55067                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker        13181                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         376749                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         684985                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2626411                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000473                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.018887                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.024935                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.015584                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.018038                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000636                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.017128                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.027147                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.020761                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.849515                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.862974                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.818548                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.843055                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.528538                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.360695                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.355875                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.438847                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000473                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.018887                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.134107                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.015584                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.084269                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000636                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.017128                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.073587                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.067981                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000473                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.018887                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.134107                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.015584                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.084269                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000636                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.017128                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.073587                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.067981                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73123.011253                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 77527.145754                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 79792.857143                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78165.620642                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 79199.492735                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 47642.787736                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10371.175676                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11169.470443                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  5424.160485                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68920.040060                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 72500.513212                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 30440.051054                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 73123.011253                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 70406.286692                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 79792.857143                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 78165.620642                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 74622.667421                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 35100.384138                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 73123.011253                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 70406.286692                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 79792.857143                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 78165.620642                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 74622.667421                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 35100.384138                       # average overall miss latency
+system.l2c.Writeback_accesses::writebacks      1547592                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1547592                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data          892                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          299                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data          473                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1664                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       133068                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        63209                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        95170                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           291447                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        21885                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker        11419                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          328515                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          647957                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        12632                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         6596                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          162109                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          292334                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker        53752                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker        12539                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          376279                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          698116                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2624133                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        21885                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker        11419                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         328515                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         647957                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        12632                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         6596                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         162109                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         292334                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker        53752                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker        12539                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         376279                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         698116                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2624133                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000350                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.022608                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.033990                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000152                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.012535                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.020984                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000781                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.015069                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.017388                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.020564                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.858744                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.836120                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.811839                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.841346                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.522552                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.447705                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.342576                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.447550                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000350                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.022608                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.134324                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.000152                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.012535                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.113251                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000781                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.015069                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.061719                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.067987                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000350                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.022608                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.134324                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.000152                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.012535                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.113251                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000781                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.015069                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.061719                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.067987                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73981.176181                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 76473.689684                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 86839.285714                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77961.772487                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 77689.526898                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 37071.384644                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10608.544000                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11567.210938                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5067.103571                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68624.462490                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71865.991320                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 32851.495964                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 73981.176181                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 69764.375026                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 86839.285714                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 77961.772487                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 73282.983615                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 33986.120585                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 73981.176181                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 69764.375026                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 86839.285714                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 77961.772487                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 73282.983615                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 33986.120585                       # average overall miss latency
  system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
  system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
  system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -653,119 +667,125 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
  system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.l2c.fast_writes                              0                       # number of fast writes performed
  system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               96958                       # number of writebacks
-system.l2c.writebacks::total                    96958                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.inst             2                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.inst         2577                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         4439                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           35                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         6451                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data        15968                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           29470                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          296                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          406                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total          702                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        21268                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        34438                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         55706                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2577                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        25707                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           35                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         6451                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        50406                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            85176                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2577                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        25707                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           35                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         6451                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        50406                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           85176                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    155734000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    288607000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2363250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    423558250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data   1065933000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1936195500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      2960296                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      4096905                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      7057201                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1193338588                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2055185326                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   3248523914                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    155734000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1481945588                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2363250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    423558250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   3121118326                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   5184719414                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    155734000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1481945588                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2363250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    423558250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   3121118326                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   5184719414                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28199786500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30478398000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  58678184500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    496533000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    763698500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1260231500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28696319500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31242096500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  59938416000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.015584                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.018038                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000636                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.017123                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.027147                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.012649                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.862974                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.818548                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.422129                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.360695                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.355875                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.187795                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.015584                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.084269                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000636                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.017123                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.073587                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.032431                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.015584                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.084269                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000636                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.017123                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.073587                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.032431                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60432.285603                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65016.219869                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65657.766238                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66754.321142                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 65700.559891                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10090.899015                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.992877                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56109.581907                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59677.836285                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 58315.512045                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60432.285603                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57647.550784                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65657.766238                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61919.579534                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 60870.660914                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60432.285603                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57647.550784                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65657.766238                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61919.579534                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 60870.660914                       # average overall mshr miss latency
+system.l2c.writebacks::writebacks               96569                       # number of writebacks
+system.l2c.writebacks::total                    96569                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         2032                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         4808                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           42                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         5670                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data        10484                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           23037                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          250                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data          384                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total          634                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        28299                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        32603                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         60902                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2032                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        33107                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker           42                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         5670                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        43087                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            83939                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2032                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        33107                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           42                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         5670                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        43087                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           83939                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        62500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    124575250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    307568500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3127250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    371081250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    683718500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1490133250                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      2500500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      3860881                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      6361381                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1578314336                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1925294585                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   3503608921                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    124575250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1885882836                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3127250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    371081250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   2609013085                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   4993742171                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        62500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    124575250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1885882836                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3127250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    371081250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   2609013085                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   4993742171                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  27997217000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30232738500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  58229955500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    537806500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    646167500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1183974000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28535023500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  30878906000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  59413929500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000152                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.012535                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.020984                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000781                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.015069                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.017388                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.009876                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.836120                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.811839                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.381010                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.447705                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.342576                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.208964                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000152                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.012535                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.113251                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000781                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.015069                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.061719                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.031987                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000152                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.012535                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.113251                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000781                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.015069                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.061719                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.031987                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61306.717520                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63970.153910                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65446.428571                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65215.423502                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 64684.344750                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10002                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10054.377604                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.723975                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55772.795364                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59052.681808                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 57528.634872                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61306.717520                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56963.265654                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65446.428571                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60552.210295                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59492.514457                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61306.717520                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56963.265654                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65446.428571                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60552.210295                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59492.514457                       # average overall mshr miss latency
  system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
  system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
  system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -776,54 +796,54 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
  system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
  system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
  system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                47571                       # number of replacements
-system.iocache.tags.tagsinuse                0.081570                       # Cycle average of tags in use
+system.iocache.tags.replacements                47569                       # number of replacements
+system.iocache.tags.tagsinuse                0.092434                       # Cycle average of tags in use
  system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47587                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47585                       # Sample count of references to valid blocks.
  system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5000192639009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.081570                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005098                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.005098                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5000571333009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.092434                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005777                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.005777                       # Average percentage of cache occupancy
  system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
  system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
  system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428634                       # Number of tag accesses
-system.iocache.tags.data_accesses              428634                       # Number of data accesses
+system.iocache.tags.tag_accesses               428616                       # Number of tag accesses
+system.iocache.tags.data_accesses              428616                       # Number of data accesses
  system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
  system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide          906                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              906                       # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          906                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               906                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          906                       # number of overall misses
-system.iocache.overall_misses::total              906                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    132202779                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    132202779                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    132202779                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    132202779                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    132202779                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    132202779                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          906                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            906                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          904                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               904                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          904                       # number of overall misses
+system.iocache.overall_misses::total              904                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    131931527                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    131931527                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    131931527                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    131931527                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    131931527                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    131931527                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
  system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
  system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          906                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             906                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          906                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            906                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          904                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             904                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          904                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            904                       # number of overall (read+write) accesses
  system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
  system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
  system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
  system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
  system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
  system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145919.182119                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 145919.182119                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145919.182119                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 145919.182119                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145919.182119                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 145919.182119                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 145941.954646                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 145941.954646                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 145941.954646                       # average overall miss latency
  system.iocache.blocked_cycles::no_mshrs           471                       # number of cycles access was blocked
  system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.iocache.blocked::no_mshrs                   39                       # number of cycles access was blocked
@@ -832,38 +852,38 @@ system.iocache.avg_blocked_cycles::no_mshrs    12.076923                       #
  system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.iocache.fast_writes                      46720                       # number of fast writes performed
  system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          740                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          740                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        28368                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        28368                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          740                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          740                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          740                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          740                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     93698779                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     93698779                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   1718205368                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   1718205368                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     93698779                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     93698779                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     93698779                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     93698779                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.816777                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.816777                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.607192                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.607192                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.816777                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.816777                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.816777                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.816777                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 126619.971622                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60568.435138                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60568.435138                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 126619.971622                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 126619.971622                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          734                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          734                       # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        22056                       # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total        22056                       # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          734                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          734                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          734                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          734                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     93740027                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     93740027                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   1329860248                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   1329860248                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     93740027                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     93740027                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     93740027                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     93740027                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.811947                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.811947                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.472089                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.472089                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.811947                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.811947                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.811947                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.811947                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60294.715633                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60294.715633                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 127711.208447                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 127711.208447                       # average overall mshr miss latency
  system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
  system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
  system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -877,567 +897,563 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
  system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
  system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
  system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq            7367165                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7366643                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13756                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13756                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          1548978                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq        28368                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1663                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1663                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296632                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296632                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            7431790                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           7431262                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13902                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13902                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback          1547592                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq        22056                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1664                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           1664                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           291447                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          291447                       # Transaction distribution
  system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1740682                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     14873990                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        71302                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       198555                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              16884529                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55700736                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213654403                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       264160                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       728920                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              270348219                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                           69633                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          4254339                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            3.011195                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.105211                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1733856                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     14997138                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        72735                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       201275                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17005004                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     55482624                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213567857                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       271280                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       749120                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              270070881                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                           66934                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          4248687                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            3.011209                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.105278                       # Request fanout histogram
  system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
  system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
  system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
  system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                4206713     98.88%     98.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  47626      1.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                4201063     98.88%     98.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  47624      1.12%    100.00% # Request fanout histogram
  system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
  system.toL2Bus.snoop_fanout::min_value              3                       # Request fanout histogram
  system.toL2Bus.snoop_fanout::max_value              4                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            4254339                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         5229007845                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4248687                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         5247340592                       # Layer occupancy (ticks)
  system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           990000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           936000                       # Layer occupancy (ticks)
  system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2442789502                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2425844552                       # Layer occupancy (ticks)
  system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4872933864                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4872344858                       # Layer occupancy (ticks)
  system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          24776404                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          24091410                       # Layer occupancy (ticks)
  system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          82986153                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          80681637                       # Layer occupancy (ticks)
  system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq              3504325                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             3504325                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57563                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              39211                       # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp        18352                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1664                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1664                       # Transaction distribution
+system.iobus.trans_dist::ReadReq              3554542                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             3554542                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57685                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              33021                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp        24664                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1687                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1687                       # Transaction distribution
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      6984892                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1154                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7085054                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1126                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27280                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27782                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      7028524                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95252                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95252                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3328                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3328                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 7127104                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      7129206                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95248                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95248                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3374                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3374                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 7227828                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3492446                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2308                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3542527                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2252                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13640                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13891                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      3520458                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6656                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6656                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  6554906                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2324808                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total      3570760                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027776                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027776                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6748                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6748                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  6605284                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2693792                       # Layer occupancy (ticks)
  system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                27000                       # Layer occupancy (ticks)
  system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 4000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
  system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              4502000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              4846000                       # Layer occupancy (ticks)
  system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                 1000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                 4000                       # Layer occupancy (ticks)
  system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
  system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
  system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                25000                       # Layer occupancy (ticks)
  system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
  system.iobus.reqLayer7.occupancy                15000                       # Layer occupancy (ticks)
  system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
  system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
  system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            143632000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy            142528000                       # Layer occupancy (ticks)
  system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              361000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              333000                       # Layer occupancy (ticks)
  system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer11.occupancy              134000                       # Layer occupancy (ticks)
  system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            11636000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            10264000                       # Layer occupancy (ticks)
  system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
  system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
  system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           256433144                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           199614020                       # Layer occupancy (ticks)
  system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy             1024000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy             1032000                       # Layer occupancy (ticks)
  system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           306163000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           303080000                       # Layer occupancy (ticks)
  system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            33668003                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            27344255                       # Layer occupancy (ticks)
  system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy              980000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1127000                       # Layer occupancy (ticks)
  system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
  system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                      1069607129                       # number of cpu cycles simulated
+system.cpu0.numCycles                       818767223                       # number of cpu cycles simulated
  system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
  system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   70538619                       # Number of instructions committed
-system.cpu0.committedOps                    143755687                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            131850662                       # Number of integer alu accesses
+system.cpu0.committedInsts                   72040073                       # Number of instructions committed
+system.cpu0.committedOps                    146798683                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            134677148                       # Number of integer alu accesses
  system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     928819                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     13976393                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   131850662                       # number of integer instructions
+system.cpu0.num_func_calls                     957492                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14259376                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   134677148                       # number of integer instructions
  system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          241989475                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         113259644                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          247199145                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         115729599                       # number of times the integer registers were written
  system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
  system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            82136389                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           54810829                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13501731                       # number of memory refs
-system.cpu0.num_load_insts                    9912408                       # Number of load instructions
-system.cpu0.num_store_insts                   3589323                       # Number of store instructions
-system.cpu0.num_idle_cycles              1016224343.330366                       # Number of idle cycles
-system.cpu0.num_busy_cycles              53382785.669634                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.049909                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.950091                       # Percentage of idle cycles
-system.cpu0.Branches                         15238819                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                94852      0.07%      0.07% # Class of executed instruction
-system.cpu0.op_class::IntAlu                130054750     90.47%     90.53% # Class of executed instruction
-system.cpu0.op_class::IntMult                   56051      0.04%     90.57% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    48845      0.03%     90.61% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.61% # Class of executed instruction
-system.cpu0.op_class::MemRead                 9912408      6.90%     97.50% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3589323      2.50%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            83822967                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           55940767                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     13836630                       # number of memory refs
+system.cpu0.num_load_insts                   10218166                       # Number of load instructions
+system.cpu0.num_store_insts                   3618464                       # Number of store instructions
+system.cpu0.num_idle_cycles              776544159.837226                       # Number of idle cycles
+system.cpu0.num_busy_cycles              42223063.162775                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.051569                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.948431                       # Percentage of idle cycles
+system.cpu0.Branches                         15573109                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                95028      0.06%      0.06% # Class of executed instruction
+system.cpu0.op_class::IntAlu                132757091     90.43%     90.50% # Class of executed instruction
+system.cpu0.op_class::IntMult                   59427      0.04%     90.54% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    51115      0.03%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::MemRead                10218166      6.96%     97.54% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3618464      2.46%    100.00% # Class of executed instruction
  system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
  system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 143756229                       # Class of executed instruction
+system.cpu0.op_class::total                 146799291                       # Class of executed instruction
  system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
  system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           869835                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.810026                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          128546541                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           870347                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           147.695736                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle     147420125000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   125.953257                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   137.567270                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   247.289498                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.246002                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.268686                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.482987                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997676                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           866413                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.840210                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          130156159                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           866925                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           150.135432                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle     149014386250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   138.994027                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   266.522548                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   105.323634                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.271473                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.520552                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.205710                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997735                       # Average percentage of cache occupancy
  system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          116                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          228                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          168                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
  system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        130310898                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       130310898                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     85798477                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     39676062                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      3072002                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      128546541                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     85798477                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     39676062                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      3072002                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       128546541                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     85798477                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     39676062                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      3072002                       # number of overall hits
-system.cpu0.icache.overall_hits::total      128546541                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       328211                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       165364                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       400424                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       893999                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       328211                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       165364                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       400424                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        893999                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       328211                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       165364                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       400424                       # number of overall misses
-system.cpu0.icache.overall_misses::total       893999                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2321256000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5686834829                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   8008090829                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2321256000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   5686834829                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   8008090829                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2321256000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   5686834829                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   8008090829                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     86126688                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     39841426                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3472426                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    129440540                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     86126688                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     39841426                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3472426                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    129440540                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     86126688                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     39841426                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3472426                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    129440540                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003811                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004151                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.115315                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.006907                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003811                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004151                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.115315                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.006907                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003811                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004151                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.115315                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.006907                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14037.251155                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14202.032918                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8957.606025                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14037.251155                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14202.032918                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8957.606025                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14037.251155                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14202.032918                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8957.606025                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4468                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        131912504                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       131912504                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     87639896                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     39531787                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2984476                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      130156159                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     87639896                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     39531787                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2984476                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       130156159                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     87639896                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     39531787                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2984476                       # number of overall hits
+system.cpu0.icache.overall_hits::total      130156159                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       328528                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       162109                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       398768                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       889405                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       328528                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       162109                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       398768                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        889405                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       328528                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       162109                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       398768                       # number of overall misses
+system.cpu0.icache.overall_misses::total       889405                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2245844750                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5606326194                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7852170944                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2245844750                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   5606326194                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7852170944                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   2245844750                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   5606326194                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7852170944                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     87968424                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     39693896                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      3383244                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    131045564                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     87968424                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     39693896                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      3383244                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    131045564                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     87968424                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     39693896                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      3383244                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    131045564                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003735                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004084                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.117866                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.006787                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003735                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004084                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.117866                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.006787                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003735                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004084                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.117866                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.006787                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.917734                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14059.117567                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8828.566226                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.917734                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14059.117567                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8828.566226                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.917734                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14059.117567                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8828.566226                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4938                       # number of cycles access was blocked
  system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              254                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              262                       # number of cycles access was blocked
  system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.590551                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.847328                       # average number of cycles each access was blocked
  system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
  system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23641                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        23641                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        23641                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        23641                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        23641                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        23641                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       165364                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       376783                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       542147                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       165364                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       376783                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       542147                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       165364                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       376783                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       542147                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1989596000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4688278233                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6677874233                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1989596000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4688278233                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6677874233                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1989596000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4688278233                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6677874233                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004151                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.108507                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004188                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004151                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.108507                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004188                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004151                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.108507                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004188                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12031.615104                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12442.913383                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12317.460454                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12031.615104                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12442.913383                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12317.460454                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12031.615104                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12442.913383                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12317.460454                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        22465                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        22465                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        22465                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        22465                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        22465                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        22465                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       162109                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       376303                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       538412                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       162109                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       376303                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       538412                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       162109                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       376303                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       538412                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1920905250                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4627637688                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6548542938                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1920905250                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4627637688                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6548542938                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1920905250                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4627637688                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6548542938                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004084                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.111225                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004109                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004084                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.111225                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.004109                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004084                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.111225                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.004109                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11849.467025                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12297.636979                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12162.698710                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11849.467025                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12297.636979                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12162.698710                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11849.467025                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12297.636979                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12162.698710                       # average overall mshr miss latency
  system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1639466                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999450                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19633257                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1639978                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            11.971659                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1637866                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999423                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19673585                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1638378                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            12.007965                       # Average number of references to valid blocks.
  system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   254.719707                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   235.128668                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data    22.151075                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.497499                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.459236                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.043264                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   126.297276                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   280.648639                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   105.053508                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.246674                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.548142                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.205183                       # Average percentage of cache occupancy
  system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
  system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          270                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          221                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
  system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88291742                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88291742                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4780114                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2623103                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4098065                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11501282                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3444198                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1705247                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2919966                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8069411                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        17741                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        11962                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        31134                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        60837                       # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8224312                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      4328350                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      7018031                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19570693                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8242053                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      4340312                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      7049165                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19631530                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       360631                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       171099                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       767926                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1299656                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       141722                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        60933                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       123702                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       326357                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       148420                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        75080                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       181895                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       405395                       # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       502353                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       232032                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       891628                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1626013                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       650773                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       307112                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1073523                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2031408                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2363215000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  13135142401                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  15498357401                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2121316122                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   4027899410                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   6149215532                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   4484531122                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  17163041811                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  21647572933                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   4484531122                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  17163041811                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  21647572933                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5140745                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2794202                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4865991                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     12800938                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3585920                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1766180                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      3043668                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8395768                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       166161                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        87042                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       213029                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       466232                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8726665                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      4560382                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7909659                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21196706                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8892826                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      4647424                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      8122688                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21662938                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.070152                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.061234                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.157815                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.101528                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.039522                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.034500                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.040642                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.038872                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.893230                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.862572                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.853851                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.869513                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.057565                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.050880                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.112726                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.076711                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.073180                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.066082                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.132164                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.093773                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13811.974354                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17104.698110                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11924.968916                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34813.912363                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32561.311943                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18841.990618                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19327.209704                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 19249.105917                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13313.284047                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 14602.266020                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15987.586490                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 10656.437768                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       138914                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         88453877                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88453877                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5010669                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      2623262                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      3898583                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       11532514                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3480346                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      1810737                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      2788314                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       8079397                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data        20263                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10587                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data        29029                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total        59879                       # number of SoftPFReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      8491015                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      4433999                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      6686897                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        19611911                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      8511278                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      4444586                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      6715926                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       19671790                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       362952                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       164891                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       772037                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1299880                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       133960                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        65129                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       126515                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       325604                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       151937                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        64294                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data       190363                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       406594                       # number of SoftPFReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       496912                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       230020                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data       898552                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1625484                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       648849                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       294314                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1088915                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2032078                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2296036750                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  11919855793                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  14215892543                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2581335822                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3855689962                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   6437025784                       # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   4877372572                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  15775545755                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  20652918327                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   4877372572                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  15775545755                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  20652918327                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5373621                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      2788153                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4670620                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     12832394                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3614306                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      1875866                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      2914829                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      8405001                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       172200                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        74881                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       219392                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       466473                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8987927                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      4664019                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7585449                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     21237395                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      9160127                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      4738900                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7804841                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     21703868                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.067543                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.059140                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.165296                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.101297                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.037064                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.034719                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.043404                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.038739                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.882329                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.858616                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.867684                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.871635                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.055287                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.049318                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.118457                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.076539                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070834                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.062106                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.139518                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.093627                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13924.572900                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15439.487736                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10936.311462                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39634.200157                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30476.148773                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19769.492340                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21204.123867                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17556.630841                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 12705.703856                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16572.003275                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14487.398700                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 10163.447627                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       128010                       # number of cycles access was blocked
  system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            26241                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            27734                       # number of cycles access was blocked
  system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     5.293777                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     4.615634                       # average number of cycles each access was blocked
  system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
  system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1548978                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1548978                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           70                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       359132                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       359202                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1638                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        26497                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        28135                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         1708                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       385629                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       387337                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         1708                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       385629                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       387337                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       171029                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       408794                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       579823                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        59295                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        97205                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       156500                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        75065                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       179480                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       254545                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       230324                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       505999                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       736323                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       305389                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       685479                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       990868                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2019901500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5830950588                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7850852088                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1912820354                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3255992760                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5168813114                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    995266500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2770573261                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3765839761                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3932721854                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9086943348                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  13019665202                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4927988354                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11857516609                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16785504963                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30674705000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33246369000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63921074000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    534053500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    811227000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1345280500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31208758500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  34057596000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65266354500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.061209                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.084010                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045295                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033572                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031937                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018640                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.862400                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.842514                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.545962                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.050505                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.063972                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.034738                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.065711                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.084391                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.045740                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11810.286560                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14263.787110                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13540.083936                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32259.387031                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33496.144849                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33027.559834                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13258.729101                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15436.668492                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.396908                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17074.737561                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17958.421554                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17682.002602                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16136.757886                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17298.147148                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16940.202896                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      1547592                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1547592                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           59                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       355847                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       355906                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1633                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        30941                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        32574                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         1692                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       386788                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       388480                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         1692                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       386788                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       388480                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       164832                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       416190                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       581022                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        63496                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        95574                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       159070                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        64293                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       186824                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       251117                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       228328                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       511764                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       740092                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       292621                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       698588                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       991209                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   1964999750                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5660700319                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7625700069                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2364352650                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3101755528                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5466108178                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    883443250                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2757990753                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3641434003                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4329352400                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   8762455847                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  13091808247                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5212795650                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11520446600                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16733242250                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30452050000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  32985877000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63437927000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    577982500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    687759500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1265742000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31030032500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33673636500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64703669000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059119                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.089108                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045278                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033849                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.032789                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018926                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.858602                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.851553                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.538331                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048955                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.067467                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.034849                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061749                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.089507                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.045670                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.227371                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13601.240585                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13124.632233                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37236.245590                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32453.967899                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34362.910530                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13740.893254                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14762.507777                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14500.945786                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18961.110333                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17122.063777                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17689.433539                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17814.154316                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16491.045652                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16881.648825                       # average overall mshr miss latency
  system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
  system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
  system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1448,376 +1464,376 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
  system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
  system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
  system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2604021576                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2606022983                       # number of cpu cycles simulated
  system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
  system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   35901808                       # Number of instructions committed
-system.cpu1.committedOps                     69778761                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             64893692                       # Number of integer alu accesses
+system.cpu1.committedInsts                   35939339                       # Number of instructions committed
+system.cpu1.committedOps                     69774923                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             64844483                       # Number of integer alu accesses
  system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     487874                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6598396                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    64893692                       # number of integer instructions
+system.cpu1.num_func_calls                     499287                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6580388                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    64844483                       # number of integer instructions
  system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          119938204                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          55974127                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          120226227                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          55826198                       # number of times the integer registers were written
  system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
  system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            36929560                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           27415142                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4838216                       # number of memory refs
-system.cpu1.num_load_insts                    3070311                       # Number of load instructions
-system.cpu1.num_store_insts                   1767905                       # Number of store instructions
-system.cpu1.num_idle_cycles              2474835372.874957                       # Number of idle cycles
-system.cpu1.num_busy_cycles              129186203.125043                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.049610                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.950390                       # Percentage of idle cycles
-system.cpu1.Branches                          7267731                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                34873      0.05%      0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 64849393     92.94%     92.99% # Class of executed instruction
-system.cpu1.op_class::IntMult                   30804      0.04%     93.03% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    25762      0.04%     93.07% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.07% # Class of executed instruction
-system.cpu1.op_class::MemRead                 3070311      4.40%     97.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1767905      2.53%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            36586824                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           27309791                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4927873                       # number of memory refs
+system.cpu1.num_load_insts                    3050339                       # Number of load instructions
+system.cpu1.num_store_insts                   1877534                       # Number of store instructions
+system.cpu1.num_idle_cycles              2477290986.248718                       # Number of idle cycles
+system.cpu1.num_busy_cycles              128731996.751282                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.049398                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.950602                       # Percentage of idle cycles
+system.cpu1.Branches                          7259898                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                35461      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 64754697     92.80%     92.86% # Class of executed instruction
+system.cpu1.op_class::IntMult                   31756      0.05%     92.90% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    25505      0.04%     92.94% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     92.94% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3050339      4.37%     97.31% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1877534      2.69%    100.00% # Class of executed instruction
  system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
  system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  69779048                       # Class of executed instruction
+system.cpu1.op_class::total                  69775292                       # Class of executed instruction
  system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
  system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               29537500                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         29537500                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           323734                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            26929505                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               26224950                       # Number of BTB hits
+system.cpu2.branchPred.lookups               29000272                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         29000272                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           311632                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26370508                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               25723888                       # Number of BTB hits
  system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.383706                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 595117                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             63666                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       155672620                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            97.547943                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 573459                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             63282                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       153009050                       # number of cpu cycles simulated
  system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
  system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          10607285                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     145694636                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   29537500                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26820067                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    143529975                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 676631                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     97153                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                5039                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             8049                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        56841                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles         4424                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          421                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3472431                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               167012                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   3661                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         154646852                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.855079                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.032629                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          10521285                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     142969715                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   29000272                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26297347                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    141031314                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 650011                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     92984                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles                4408                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             9006                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        47091                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles         2529                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          579                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3383247                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               163781                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   3234                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         152033550                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.852472                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.031588                       # Number of instructions fetched each cycle (Total)
  system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                98720699     63.84%     63.84% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  840447      0.54%     64.38% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23990695     15.51%     79.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  599923      0.39%     80.28% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  812589      0.53%     80.81% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  861055      0.56%     81.36% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  574182      0.37%     81.73% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  718315      0.46%     82.20% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27528947     17.80%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                97124192     63.88%     63.88% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  819598      0.54%     64.42% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23594190     15.52%     79.94% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  577537      0.38%     80.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  790978      0.52%     80.84% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  823076      0.54%     81.38% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  560198      0.37%     81.75% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  693420      0.46%     82.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27050361     17.79%    100.00% # Number of instructions fetched each cycle (Total)
  system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
  system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
  system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           154646852                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.189741                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.935904                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                10277789                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             95381782                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 22559618                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              5904125                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                338966                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             283871353                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                338966                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                12885148                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               76664692                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4829048                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 25619792                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             14124701                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             282624473                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents               211024                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               6375709                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 73879                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               5159969                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          337473501                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            616062521                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       378507156                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups               50                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            325128635                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                12344864                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            162095                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        163797                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 28599466                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6606628                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3716011                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           425441                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          346966                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 280674873                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             430305                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                278581977                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued           102725                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        8814114                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     13599788                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         65362                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    154646852                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.801407                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.400759                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           152033550                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.189533                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.934387                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 9712542                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             92934302                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 23280371                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              5017317                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                325657                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             278875678                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                325657                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                11857648                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               75889768                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       4419845                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 25919685                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             12857653                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             277706863                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents               221466                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               5888159                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 42783                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               4808995                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands          331833488                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            605194394                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       371618079                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups               36                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            320107208                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                11726280                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            151218                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        152719                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 24489304                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6338862                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3553328                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           367719                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          319565                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 275826769                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             413139                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                273878584                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            98557                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        8364175                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     12972199                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         61453                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    152033550                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.801435                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.398557                       # Number of insts issued each cycle
  system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           91425932     59.12%     59.12% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            5392264      3.49%     62.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3912324      2.53%     65.14% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            4126244      2.67%     67.80% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           21795400     14.09%     81.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            3071037      1.99%     83.88% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           24235245     15.67%     99.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             469170      0.30%     99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             219236      0.14%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           89826062     59.08%     59.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            5325607      3.50%     62.59% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3883778      2.55%     65.14% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            3618974      2.38%     67.52% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           22318323     14.68%     82.20% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            2568868      1.69%     83.89% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           23837030     15.68%     99.57% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             450577      0.30%     99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             204331      0.13%    100.00% # Number of insts issued each cycle
  system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
  system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
  system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      154646852                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      152033550                       # Number of insts issued each cycle
  system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                2310389     89.01%     89.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                   246      0.01%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                223101      8.59%     97.61% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                62004      2.39%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                1765790     86.71%     86.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     6      0.00%     86.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                     95      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                213483     10.48%     97.20% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                57008      2.80%    100.00% # attempts to use FU when none available
  system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
  system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            76436      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            268041478     96.22%     96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               58746      0.02%     96.26% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                49744      0.02%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             6933130      2.49%     98.77% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3422443      1.23%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            75484      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            263736524     96.30%     96.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               54819      0.02%     96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                47031      0.02%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             6686249      2.44%     98.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3278477      1.20%    100.00% # Type of FU issued
  system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
  system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             278581977                       # Type of FU issued
-system.cpu2.iq.rate                          1.789537                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    2595740                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.009318                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         714509188                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        289923619                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    276984093                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                 82                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes                98                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses           18                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             281101244                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                     37                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          733638                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             273878584                       # Type of FU issued
+system.cpu2.iq.rate                          1.789950                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    2036382                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.007435                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         701925596                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        284608270                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    272313229                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                 61                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes                68                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             275839453                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                     29                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          685704                       # Number of loads that had data forwarded from stores
  system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1227908                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         6601                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         5025                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       667461                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1161006                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         6104                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         4803                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       634153                       # Number of stores squashed
  system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
  system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       754863                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        24022                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       755552                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        21313                       # Number of times an access to memory failed due to the cache being blocked
  system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                338966                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               71689555                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              1628683                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          281105178                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            39439                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6606628                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3716011                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            250069                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                194031                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              1131651                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          5025                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        186633                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       188127                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              374760                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            278001109                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6795315                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           530943                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                325657                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               70767994                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              1741893                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          276239908                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            40444                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6338884                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3553328                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            236248                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                194416                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              1250638                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          4803                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        177191                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       184398                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              361589                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            273320009                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              6554812                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           510377                       # Number of squashed instructions skipped in execute
  system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
  system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    10133053                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                28226522                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3337738                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.785806                       # Inst execution rate
-system.cpu2.iew.wb_sent                     277806882                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    276984111                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                215977189                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                354208085                       # num instructions consuming a value
+system.cpu2.iew.exec_refs                     9748811                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                27755327                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3193999                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.786300                       # Inst execution rate
+system.cpu2.iew.wb_sent                     273134840                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    272313245                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                212432379                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                348339663                       # num instructions consuming a value
  system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.779273                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.609747                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.779720                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.609843                       # average fanout of values written-back
  system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        9156375                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         364943                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           326343                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    153280377                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.774187                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.653000                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        8691419                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         351686                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           314047                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    150733678                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.774964                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.652543                       # Number of insts commited each cycle
  system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     95267512     62.15%     62.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4211429      2.75%     64.90% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1288351      0.84%     65.74% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24928908     16.26%     82.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       992667      0.65%     82.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       656859      0.43%     83.08% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       436979      0.29%     83.37% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23484943     15.32%     98.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2012729      1.31%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     93656646     62.13%     62.13% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4148238      2.75%     64.89% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1235888      0.82%     65.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24514613     16.26%     81.97% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4      1002757      0.67%     82.63% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       665638      0.44%     83.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       467092      0.31%     83.39% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23101150     15.33%     98.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      1941656      1.29%    100.00% # Number of insts commited each cycle
  system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
  system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
  system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    153280377                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           137795324                       # Number of instructions committed
-system.cpu2.commit.committedOps             271948125                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    150733678                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           135526613                       # Number of instructions committed
+system.cpu2.commit.committedOps             267546921                       # Number of ops (including micro ops) committed
  system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8427269                       # Number of memory references committed
-system.cpu2.commit.loads                      5378719                       # Number of loads committed
-system.cpu2.commit.membars                     165391                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27813078                       # Number of branches committed
+system.cpu2.commit.refs                       8097053                       # Number of memory references committed
+system.cpu2.commit.loads                      5177878                       # Number of loads committed
+system.cpu2.commit.membars                     162019                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27358633                       # Number of branches committed
  system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                248363308                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              444774                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        44974      0.02%      0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       263371453     96.85%     96.86% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          56553      0.02%     96.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           47876      0.02%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        5378719      1.98%     98.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       3048550      1.12%    100.00% # Class of committed instruction
+system.cpu2.commit.int_insts                244351653                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              425746                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        44568      0.02%      0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       259307312     96.92%     96.94% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          52493      0.02%     96.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           45495      0.02%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5177878      1.94%     98.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2919175      1.09%    100.00% # Class of committed instruction
  system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
  system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        271948125                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              2012729                       # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total        267546921                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              1941656                       # number cycles where commit BW limit reached
  system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   432344700                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  563581737                       # The number of ROB writes
-system.cpu2.timesIdled                         114304                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1025768                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4904031691                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  137795324                       # Number of Instructions Simulated
-system.cpu2.committedOps                    271948125                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.129738                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.129738                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.885161                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.885161                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               370036745                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              221903617                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    72874                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   72912                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                140867740                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               108480868                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               90412070                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                138782                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                   425004820                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  553782312                       # The number of ROB writes
+system.cpu2.timesIdled                         113608                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                         975500                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4910108147                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  135526613                       # Number of Instructions Simulated
+system.cpu2.committedOps                    267546921                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.128996                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.128996                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.885742                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.885742                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               363608614                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              218247524                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    72984                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                138904210                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               106846664                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               88678814                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                129757                       # number of misc regfile writes
  system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
  system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
  
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal

index 72fbd3738152de9ab8b322b32b0b46337e637c67..2c13ee1330d520b92a9388b30bc1a7d3ab982356 100644 (file)
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
@@ -4,6 +4,7 @@ BIOS-provided physical RAM map:
   BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)\r
   BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)\r
   BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
+ BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)\r
   BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)\r
  end_pfn_map = 1048576\r
  kernel direct mapping tables up to 100000000 @ 8000-d000\r
@@ -23,18 +24,18 @@ Setting APIC routing to flat
  Processors: 1\r
  swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000\r
  swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000\r
-Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)\r
-Built 1 zonelists.  Total pages: 30612\r
+Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)\r
+Built 1 zonelists.  Total pages: 30610\r
  Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
  Initializing CPU#0\r
  PID hash table entries: 512 (order: 9, 4096 bytes)\r
-time.c: Detected 1999.986 MHz processor.\r
+time.c: Detected 2000.002 MHz processor.\r
  Console: colour dummy device 80x25\r
  console handover: boot [earlyser0] -> real [ttyS0]\r
  Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
  Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
  Checking aperture...\r
-Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)\r
+Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)\r
  Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
  Mount-cache hash table entries: 256\r
  CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
@@ -44,7 +45,7 @@ ACPI: Core revision 20070126
  ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
  ACPI: Unable to load the System Description Tables\r
  Using local APIC timer interrupts.\r
-result 7812464\r
+result 7812527\r
  Detected 7.812 MHz APIC timer.\r
  NET: Registered protocol family 16\r
  PCI: Using configuration type 1\r
@@ -56,6 +57,7 @@ usbcore: registered new interface driver usbfs
  usbcore: registered new interface driver hub\r
  usbcore: registered new device driver usb\r
  PCI: Probing PCI hardware\r
+PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16\r
  PCI-GART: No AMD northbridge found.\r
  NET: Registered protocol family 2\r
  Time: tsc clocksource has been installed.\r
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini

index ccf2bc154284441df2e0d1abee9099b6e08b63a4..12828101adc1e71ab03f5d5e961cf0dbb5ea2349 100644 (file)
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -16,10 +16,10 @@ cache_line_size=64
  clk_domain=system.clk_domain
  eventq_index=0
  hypervisor_addr=1099243257856
-hypervisor_bin=/dist/m5/system/binaries/q_new.bin
+hypervisor_bin=/scratch/nilay/GEM5/system/binaries/q_new.bin
  hypervisor_desc=system.hypervisor_desc
  hypervisor_desc_addr=133446500352
-hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
+hypervisor_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-hv.bin
  init_param=0
  kernel=
  kernel_addr_check=true
@@ -27,19 +27,19 @@ load_addr_mask=1099511627775
  load_offset=0
  mem_mode=atomic
  mem_ranges=1048576:68157439 2147483648:2415919103
-memories=system.hypervisor_desc system.physmem1 system.partition_desc system.physmem0 system.rom system.nvram
+memories=system.nvram system.physmem1 system.hypervisor_desc system.partition_desc system.physmem0 system.rom
  num_work_ids=16
  nvram=system.nvram
  nvram_addr=133429198848
-nvram_bin=/dist/m5/system/binaries/nvram1
+nvram_bin=/scratch/nilay/GEM5/system/binaries/nvram1
  openboot_addr=1099243716608
-openboot_bin=/dist/m5/system/binaries/openboot_new.bin
+openboot_bin=/scratch/nilay/GEM5/system/binaries/openboot_new.bin
  partition_desc=system.partition_desc
  partition_desc_addr=133445976064
-partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
-readfile=/z/stever/hg/gem5/tests/halt.sh
+partition_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-md.bin
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
  reset_addr=1099243192320
-reset_bin=/dist/m5/system/binaries/reset_new.bin
+reset_bin=/scratch/nilay/GEM5/system/binaries/reset_new.bin
  rom=system.rom
  symbolfile=
  work_begin_ckpt_count=0
@@ -160,7 +160,7 @@ table_size=65536
  [system.disk0.image.child]
  type=RawDiskImage
  eventq_index=0
-image_file=/dist/m5/system/disks/disk.s10hw2
+image_file=/scratch/nilay/GEM5/system/disks/disk.s10hw2
  read_only=true
  
  [system.dvfs_handler]
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json

index 300aaf6afe628c4966b134db6358dc7da9655111..f3e5c9bf363b0dffe0214307f7c5d0c25924811f 100644 (file)
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
@@ -471,7 +471,7 @@
              }
          }, 
          "symbolfile": "", 
-        "readfile": "/z/stever/hg/gem5/tests/halt.sh", 
+        "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", 
          "hypervisor_addr": 1099243257856, 
          "mem_ranges": [
              "1048576:68157439", 
@@ -479,17 +479,17 @@
          ], 
          "cxx_class": "SparcSystem", 
          "load_offset": 0, 
-        "reset_bin": "/dist/m5/system/binaries/reset_new.bin", 
+        "reset_bin": "/scratch/nilay/GEM5/system/binaries/reset_new.bin", 
          "openboot_addr": 1099243716608, 
          "work_end_ckpt_count": 0, 
          "nvram_addr": 133429198848, 
          "memories": [
-            "system.hypervisor_desc", 
+            "system.nvram", 
              "system.physmem1", 
+            "system.hypervisor_desc", 
              "system.partition_desc", 
              "system.physmem0", 
-            "system.rom", 
-            "system.nvram"
+            "system.rom"
          ], 
          "work_begin_ckpt_count": 0, 
          "partition_desc": {
@@ -639,8 +639,8 @@
              "type": "DVFSHandler"
          }, 
          "work_end_exit_count": 0, 
-        "hypervisor_desc_bin": "/dist/m5/system/binaries/1up-hv.bin", 
-        "openboot_bin": "/dist/m5/system/binaries/openboot_new.bin", 
+        "hypervisor_desc_bin": "/scratch/nilay/GEM5/system/binaries/1up-hv.bin", 
+        "openboot_bin": "/scratch/nilay/GEM5/system/binaries/openboot_new.bin", 
          "voltage_domain": {
              "name": "voltage_domain", 
              "eventq_index": 0, 
@@ -700,7 +700,7 @@
          "work_cpus_ckpt_count": 0, 
          "work_begin_exit_count": 0, 
          "path": "system", 
-        "hypervisor_bin": "/dist/m5/system/binaries/q_new.bin", 
+        "hypervisor_bin": "/scratch/nilay/GEM5/system/binaries/q_new.bin", 
          "cpu_clk_domain": {
              "name": "cpu_clk_domain", 
              "clock": [
@@ -714,12 +714,12 @@
              "type": "SrcClockDomain", 
              "domain_id": -1
          }, 
-        "nvram_bin": "/dist/m5/system/binaries/nvram1", 
+        "nvram_bin": "/scratch/nilay/GEM5/system/binaries/nvram1", 
          "mem_mode": "atomic", 
          "name": "system", 
          "init_param": 0, 
          "type": "SparcSystem", 
-        "partition_desc_bin": "/dist/m5/system/binaries/1up-md.bin", 
+        "partition_desc_bin": "/scratch/nilay/GEM5/system/binaries/1up-md.bin", 
          "load_addr_mask": 1099511627775, 
          "cpu": {
              "do_statistics_insts": true, 
@@ -825,7 +825,7 @@
                      "eventq_index": 0, 
                      "cxx_class": "RawDiskImage", 
                      "path": "system.disk0.image.child", 
-                    "image_file": "/dist/m5/system/disks/disk.s10hw2", 
+                    "image_file": "/scratch/nilay/GEM5/system/disks/disk.s10hw2", 
                      "type": "RawDiskImage"
                  }, 
                  "path": "system.disk0.image", 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini

index 68be94d238a59023e36e3669961068f94ab7c14b..04ace1eeb21fedcb27ba4da279515cfee571c566 100644 (file)
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -763,6 +764,7 @@ ppid=99
  simpoint=55300000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini

index 4a5a11c6ec07dd2fb1cc1bca3c4508010cae63ff..8fe365c4e232e85c141b6c91489781c87066cd54 100644 (file)
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
  type=DerivO3CPU
  children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu.fuPool
  function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
  
  [system.cpu.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu.dcache]
  type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
  sequential_access=false
-size=262144
+size=32768
  system=system
  tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu.dcache_port
  mem_side=system.cpu.toL2Bus.slave[1]
  
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
  eventq_index=0
  hit_latency=2
  sequential_access=false
-size=262144
+size=32768
  
  [system.cpu.dstage2_mmu]
  type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
  
  [system.cpu.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
  eventq_index=0
  
  [system.cpu.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu.fuPool.FUList0.opList
  
@@ -249,10 +249,10 @@ opLat=1
  
  [system.cpu.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
  
  [system.cpu.fuPool.FUList1.opList0]
  type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
  [system.cpu.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
  
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
  
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
  
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu.icache]
  type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
-size=131072
+size=32768
  system=system
  tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
-size=131072
+size=32768
  
  [system.cpu.interrupts]
  type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
  
  [system.cpu.l2cache]
  type=BaseCache
-children=tags
+children=prefetcher tags
  addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=20
+hit_latency=12
  is_top_level=false
  max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  system=system
  tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.toL2Bus.master[0]
  mem_side=system.membus.slave[1]
  
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
  [system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=20
+hit_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -712,6 +688,7 @@ ppid=99
  simpoint=55300000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini

index 1ac296d577358d1bc7952426fb579f174fd14d91..392920ac8a1b6a55e53b990ef3c7a9a8b1c7b738 100644 (file)
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
  simpoint=55300000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini

index 091559190ca66ba62ac3b552a2406f9f1c7338b4..e662df1f594c8f1819125ae7b8ab8e11c99fc7ca 100644 (file)
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -332,6 +333,7 @@ ppid=99
  simpoint=55300000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini

index 84ab5e292026bece6e1e46b1438e903a96d2739b..5a88776552761143065160d1701427a7c9bdd00b 100644 (file)
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
  simpoint=55300000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini

index b0f5cdf9bcba642287e3d9247cf7c5dcf01cafd9..e9a50bebb8915cc236f26c5f09bfd97aff8eb412 100644 (file)
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -233,6 +234,7 @@ ppid=99
  simpoint=55300000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini

index 098c34f7979a72ab82fce16539ffd74ead221d90..c3e1a19788e921e7115ae0052ec6c45be05f1a1f 100644 (file)
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -614,10 +614,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -647,6 +648,7 @@ ppid=99
  simpoint=55300000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -687,6 +715,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -700,19 +729,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini

index d838f1c8737b04e204ab0a59eaf2fec0c7c4cb9b..fbecda938306f429a12ea3d4a77156f0b0d04b43 100644 (file)
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
  simpoint=55300000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini

index 31f143ff4cc16e2e760bc566632ff557067b3dfe..1e2ff91f9039e18fc57ac8023f3da7033e8305d5 100644 (file)
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -267,6 +268,7 @@ ppid=99
  simpoint=55300000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini

index a5f2c0f8eced39061a355f3f327ccff158b220fc..956669942eacb98db4f7ada964ee353997caba22 100644 (file)
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -665,6 +666,7 @@ ppid=99
  simpoint=114600000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini

index 35eb71fc6612f4fbf32bc515f801f2865bcecc44..2fe2a523a9aa4807c61301d3d32a1829f838db4a 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -763,6 +764,7 @@ ppid=99
  simpoint=114600000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini

index 3e9c4c1da9cd67fece1b6c0ac682b907abfc04cb..8a55cdea8701582ad0798501280c966d5a398d4c 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
  type=DerivO3CPU
  children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu.fuPool
  function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
  
  [system.cpu.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu.dcache]
  type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
  sequential_access=false
-size=262144
+size=32768
  system=system
  tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu.dcache_port
  mem_side=system.cpu.toL2Bus.slave[1]
  
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
  eventq_index=0
  hit_latency=2
  sequential_access=false
-size=262144
+size=32768
  
  [system.cpu.dstage2_mmu]
  type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
  
  [system.cpu.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
  eventq_index=0
  
  [system.cpu.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu.fuPool.FUList0.opList
  
@@ -249,10 +249,10 @@ opLat=1
  
  [system.cpu.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
  
  [system.cpu.fuPool.FUList1.opList0]
  type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
  [system.cpu.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
  
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
  
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
  
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu.icache]
  type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
-size=131072
+size=32768
  system=system
  tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
-size=131072
+size=32768
  
  [system.cpu.interrupts]
  type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
  
  [system.cpu.l2cache]
  type=BaseCache
-children=tags
+children=prefetcher tags
  addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=20
+hit_latency=12
  is_top_level=false
  max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  system=system
  tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.toL2Bus.master[0]
  mem_side=system.membus.slave[1]
  
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
  [system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=20
+hit_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -712,6 +688,7 @@ ppid=99
  simpoint=114600000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini

index 1b406eef61d83da31bbb66f9c9f873d44f469ae9..0288139dc949d0e81500d59fe82a5dcddcdeaadb 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
  simpoint=114600000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini

index dd4a9278626835ca44aa925e5c8b52da462bc232..abc8be573aaa7178cc0470f6b82d0cf0c75f78e4 100644 (file)
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -332,6 +333,7 @@ ppid=99
  simpoint=114600000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini

index 5f45842db219a655c4f2000e41aaa1e5f7690602..9577cfdf69738e4001b628956e44e9aba29e4662 100644 (file)
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -614,10 +614,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -647,6 +648,7 @@ ppid=99
  simpoint=114600000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -687,6 +715,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -700,19 +729,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini

index 8134f7b0ee1efba36c72ad091b14082f7a751cd5..156b7eda7dae3c009d10ebd132d67f764f2d46f0 100644 (file)
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
  simpoint=114600000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini

index 2b0e6b6be8a8faae82c23ba8fa2854fd91ad3bab..d1dba8bc24cdc8b77e1a273f26e82538cfaa97ca 100644 (file)
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -267,6 +268,7 @@ ppid=99
  simpoint=114600000000
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini

index 383c5c9aac358440a1d3932ef5d11346044529e2..f0acfeb88a64cd99f8b3fcfe2c7c20359f24c72e 100644 (file)
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -665,6 +666,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini

index 536d6ad31ed9276f54137846ab7df011a5a833d4..c0739097ebc1244f36957f91483d8dedf4b1fa99 100644 (file)
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
  eventq_index=0
  init_param=0
  kernel=
+kernel_addr_check=true
  load_addr_mask=1099511627775
  load_offset=0
  mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -603,7 +605,7 @@ env=
  errout=cerr
  euid=100
  eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
  gid=100
  input=cin
  max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini

index 0aab988e519a196bfd3be56c92a0b14ae0f5d526..44bc5cf02b29fb1f44f6a608078c36a3a7ccd6ee 100644 (file)
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini

index 5569f2848c0ec716de7a3006e798ccf2f905ca37..601735401862c3c403dadc7a14ab12600d7e1076 100644 (file)
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -234,6 +235,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini

index 3da78afde3f8acceaefae964029c8103ab12557c..c190aab09895ad21b1c0b94539b0dc557d5830b7 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -763,6 +764,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini

index 521f5fb700d911cb69335dabcff89e70764a2b7a..a21e9064576e645805a6f0896db7db2b0d57a7a3 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
  type=DerivO3CPU
  children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu.fuPool
  function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
  
  [system.cpu.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu.dcache]
  type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
  sequential_access=false
-size=262144
+size=32768
  system=system
  tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu.dcache_port
  mem_side=system.cpu.toL2Bus.slave[1]
  
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
  eventq_index=0
  hit_latency=2
  sequential_access=false
-size=262144
+size=32768
  
  [system.cpu.dstage2_mmu]
  type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
  
  [system.cpu.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
  eventq_index=0
  
  [system.cpu.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu.fuPool.FUList0.opList
  
@@ -249,10 +249,10 @@ opLat=1
  
  [system.cpu.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
  
  [system.cpu.fuPool.FUList1.opList0]
  type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
  [system.cpu.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
  
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
  
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
  
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu.icache]
  type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
-size=131072
+size=32768
  system=system
  tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
-size=131072
+size=32768
  
  [system.cpu.interrupts]
  type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
  
  [system.cpu.l2cache]
  type=BaseCache
-children=tags
+children=prefetcher tags
  addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=20
+hit_latency=12
  is_top_level=false
  max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  system=system
  tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.toL2Bus.master[0]
  mem_side=system.membus.slave[1]
  
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
  [system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=20
+hit_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -712,6 +688,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini

index ea25a257f06b623d2590e25a0602fe47f19ebb6d..a03e92cf3597db69b65b6220f9653971eaf9afa4 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini

index e7e094253b49b88b7580f6efb6ba16c4619fd7a5..f7026168d26542c6794136f8545a3dfb08916684 100644 (file)
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -332,6 +333,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini

index acd11e636bd5b10fbcc64a8f23b0d0f154e467cf..503aa08b6d4e24deb81659dd9572926e6b8960a2 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -648,7 +649,7 @@ eventq_index=0
  
  [system.cpu.workload]
  type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
  cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing
  egid=100
  env=
@@ -665,6 +666,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini

index a624ec61c2c188c6dcef6c447aebaae69fb1ef78..3d200442cb7305aa0418aa507ccaccd4822b64e9 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
  eventq_index=0
  init_param=0
  kernel=
+kernel_addr_check=true
  load_addr_mask=1099511627775
  load_offset=0
  mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -596,14 +598,14 @@ eventq_index=0
  
  [system.cpu.workload]
  type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
  cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
  egid=100
  env=
  errout=cerr
  euid=100
  eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
  gid=100
  input=cin
  max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini

index 7c82d017b5b9c29afdddcadcd9444e88c9f61795..02a01f5dbc5c89225e8d9a62c4a943bbc6f350b0 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -108,7 +105,7 @@ eventq_index=0
  
  [system.cpu.workload]
  type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
  cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
  egid=100
  env=
@@ -125,6 +122,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini

index 354d6da6a31cd26cf8f923cb59af1ef199c1dda9..48df53b706794687f370500d52dd6842b8d64ffe 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -217,7 +218,7 @@ eventq_index=0
  
  [system.cpu.workload]
  type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
  cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
  egid=100
  env=
@@ -234,6 +235,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini

index 901264c7e0e8955ef490fd6b7fb758558daf7251..c01955b007f8fb4d74076f04f49fbf236a4a2e80 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -746,7 +747,7 @@ eventq_index=0
  
  [system.cpu.workload]
  type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
  cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
  egid=100
  env=
@@ -763,6 +764,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini

index db65c79efa1cdb728720d56caf0b1fa018d4c569..3db3f48e914d913f3e9fb32767c6dd13d7877f6d 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
  type=DerivO3CPU
  children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu.fuPool
  function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
  
  [system.cpu.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu.dcache]
  type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
  sequential_access=false
-size=262144
+size=32768
  system=system
  tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu.dcache_port
  mem_side=system.cpu.toL2Bus.slave[1]
  
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
  eventq_index=0
  hit_latency=2
  sequential_access=false
-size=262144
+size=32768
  
  [system.cpu.dstage2_mmu]
  type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
  
  [system.cpu.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
  eventq_index=0
  
  [system.cpu.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu.fuPool.FUList0.opList
  
@@ -249,10 +249,10 @@ opLat=1
  
  [system.cpu.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
  
  [system.cpu.fuPool.FUList1.opList0]
  type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
  [system.cpu.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
  
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
  
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
  
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu.icache]
  type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
-size=131072
+size=32768
  system=system
  tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
-size=131072
+size=32768
  
  [system.cpu.interrupts]
  type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
  
  [system.cpu.l2cache]
  type=BaseCache
-children=tags
+children=prefetcher tags
  addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=20
+hit_latency=12
  is_top_level=false
  max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  system=system
  tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.toL2Bus.master[0]
  mem_side=system.membus.slave[1]
  
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
  [system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=20
+hit_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -695,7 +671,7 @@ eventq_index=0
  
  [system.cpu.workload]
  type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
  cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
  egid=100
  env=
@@ -712,6 +688,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

index 183fc2417fa1d26af21d40c9a46890fa13b4ec67..b27ae5a40b173e5c7ed7dcbe685dff4c7013eda5 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.407884                       # Nu
  sim_ticks                                407883784500                       # Number of ticks simulated
  final_tick                               407883784500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
  sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  91837                       # Simulator instruction rate (inst/s)
-host_op_rate                                   113063                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               58469822                       # Simulator tick rate (ticks/s)
-host_mem_usage                                2565440                       # Number of bytes of host memory used
-host_seconds                                  6975.97                       # Real time elapsed on the host
+host_inst_rate                                  65117                       # Simulator instruction rate (inst/s)
+host_op_rate                                    80168                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               41458433                       # Simulator tick rate (ticks/s)
+host_mem_usage                                2600432                       # Number of bytes of host memory used
+host_seconds                                  9838.38                       # Real time elapsed on the host
  sim_insts                                   640649298                       # Number of instructions simulated
  sim_ops                                     788724957                       # Number of ops (including micro ops) simulated
  system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -420,7 +420,7 @@ system.cpu.numCycles                        815767570                       # nu
  system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
  system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
  system.cpu.fetch.icacheStallCycles           84062545                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1200075863                       # Number of instructions fetch has processed
+system.cpu.fetch.Insts                     1200075862                       # Number of instructions fetch has processed
  system.cpu.fetch.Branches                   233961455                       # Number of branches that fetch encountered
  system.cpu.fetch.predictedBranches          133292629                       # Number of branches that fetch has predicted taken
  system.cpu.fetch.Cycles                     716015819                       # Number of cycles fetch has run and was not squashing or blocked
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini

index b0a290b06d5d0a37967c26994c3d54ba5b1d72a8..7eb73e4668237a0526020326a105ef0e13366ee9 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -206,7 +203,7 @@ eventq_index=0
  
  [system.cpu.workload]
  type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
  cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
  egid=100
  env=
@@ -223,6 +220,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini

index e3c2da1c2ca8a23d397b0cf38faea95dfda05ef7..0c1f952a4408baf5ab8d56ca398d7af8c307866b 100644 (file)
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -315,7 +316,7 @@ eventq_index=0
  
  [system.cpu.workload]
  type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
+cmd=perlbmk -I. -I lib mdred.makerand.pl
  cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
  egid=100
  env=
@@ -332,6 +333,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini

index d2cfbc5748cfe8230d01dfdb2c0b4664a5349c38..e4bee3f353cf5a6c1b42c92cf0e94a665df03ddf 100644 (file)
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -665,6 +666,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini

index e46a676ebe617986098be2b43e1846a91959a2cc..72bc50e356e00d28460590960620bfd5a4e620f1 100644 (file)
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
  eventq_index=0
  init_param=0
  kernel=
+kernel_addr_check=true
  load_addr_mask=1099511627775
  load_offset=0
  mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -603,7 +605,7 @@ env=
  errout=cerr
  euid=100
  eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
  gid=100
  input=cin
  max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini

index 34c305ae5e3708403026b229ee64efd1ce7c5fa4..bc26b879f792b8296ff9ad5adc49aed340e37c61 100644 (file)
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini

index d2c7c290fb8c8e15c64fe0ca05687121bf8d9ce0..5ccaad7e069bffef3b7f2356fc377847d1d0abe4 100644 (file)
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -234,6 +235,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini

index 6ff93edf56b2cdc2776fde820539c67af2e594e0..fd6ea1264be8d3687aa092583acf592b3c917aca 100644 (file)
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -763,6 +764,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini

index 11661d187fe9768a61732225da9006c531f97c7e..6bff9ac08ef8876124a178a4da7146a6ef181af5 100644 (file)
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
  type=DerivO3CPU
  children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu.fuPool
  function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
  
  [system.cpu.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu.dcache]
  type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
  sequential_access=false
-size=262144
+size=32768
  system=system
  tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu.dcache_port
  mem_side=system.cpu.toL2Bus.slave[1]
  
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
  eventq_index=0
  hit_latency=2
  sequential_access=false
-size=262144
+size=32768
  
  [system.cpu.dstage2_mmu]
  type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
  
  [system.cpu.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
  eventq_index=0
  
  [system.cpu.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu.fuPool.FUList0.opList
  
@@ -249,10 +249,10 @@ opLat=1
  
  [system.cpu.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
  
  [system.cpu.fuPool.FUList1.opList0]
  type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
  [system.cpu.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
  
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
  
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
  
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu.icache]
  type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
-size=131072
+size=32768
  system=system
  tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
-size=131072
+size=32768
  
  [system.cpu.interrupts]
  type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
  
  [system.cpu.l2cache]
  type=BaseCache
-children=tags
+children=prefetcher tags
  addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=20
+hit_latency=12
  is_top_level=false
  max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  system=system
  tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.toL2Bus.master[0]
  mem_side=system.membus.slave[1]
  
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
  [system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=20
+hit_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -712,6 +688,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini

index 7a91447596b8eba4295dff6855706c4629d73ed8..f73c6b1289877f7599a44d64261d64ac2e766225 100644 (file)
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini

index 0709f1643552e4deb99fa33c87dc3ae943a00450..8d05feb2e2d072ae2bc96c02aab0b7a842b84d61 100644 (file)
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -332,6 +333,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini

index d88b9c728fa3332a5d6b97f4247a5ef4fafad63c..5fee4647b86204b6651a253712dda3cb38dd1e20 100644 (file)
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini

index 0fe5ca901faa76a86df6024789937bf8f37a7fe4..5186e7456a14b3294d68a5099d2ef38b23d34bb6 100644 (file)
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -233,6 +234,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini

index 581902389adc19356cd2012f3a5194250bf3aaf0..706f923ddef0fee9a1e00938f5a1c895ca22fb99 100644 (file)
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -665,6 +666,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini

index a124b2ba9697ae8c493312a5c23081e10957f3ee..cfff7eb6d9f771864846c70fb4d34848cab69adb 100644 (file)
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
  eventq_index=0
  init_param=0
  kernel=
+kernel_addr_check=true
  load_addr_mask=1099511627775
  load_offset=0
  mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -603,7 +605,7 @@ env=
  errout=cerr
  euid=100
  eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
  gid=100
  input=cin
  max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini

index a048badbc7e9bc7bc4c38921eb2c31f335beed6d..2e63bb33be7831d4713ba497216855998fafad92 100644 (file)
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini

index d3adad404110ce70ab21edd30a9bae7938f88df1..fc2fe20b8777c9c8aab354eecb5a5df05303c72a 100644 (file)
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -234,6 +235,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini

index 0d07c139df226d67c08299ba3f949381d8f60417..55081d3ef96547fee53fce25d9ab944fe2851b95 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -763,6 +764,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini

index d2257e41a22f0d27f155957921b61a137c2dd505..d573e889816029a32fbc3a2ab5e1019649b3ee57 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
  type=DerivO3CPU
  children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu.fuPool
  function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
  
  [system.cpu.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu.dcache]
  type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
  sequential_access=false
-size=262144
+size=32768
  system=system
  tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu.dcache_port
  mem_side=system.cpu.toL2Bus.slave[1]
  
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
  eventq_index=0
  hit_latency=2
  sequential_access=false
-size=262144
+size=32768
  
  [system.cpu.dstage2_mmu]
  type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
  
  [system.cpu.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
  eventq_index=0
  
  [system.cpu.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu.fuPool.FUList0.opList
  
@@ -249,10 +249,10 @@ opLat=1
  
  [system.cpu.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
  
  [system.cpu.fuPool.FUList1.opList0]
  type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
  [system.cpu.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
  
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
  
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
  
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu.icache]
  type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
-size=131072
+size=32768
  system=system
  tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
-size=131072
+size=32768
  
  [system.cpu.interrupts]
  type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
  
  [system.cpu.l2cache]
  type=BaseCache
-children=tags
+children=prefetcher tags
  addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=20
+hit_latency=12
  is_top_level=false
  max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  system=system
  tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.toL2Bus.master[0]
  mem_side=system.membus.slave[1]
  
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
  [system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=20
+hit_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -712,6 +688,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini

index ec3a0574defc4b45c45140a1b9718c3b6e22d56e..c5adbf84c3ae4b56799fea43731b1d62a6c2c6a1 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini

index 3e6b06c1316fcf21f072738a5504bea117e44276..3bcac58f7c01a5aaa06c2cf5a99905fabd5c12a2 100644 (file)
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -332,6 +333,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini

index abb41bc3751beba88354348d4791314c21c25b7f..36079bdafeacc86f015a997bc6759a79f0c9353d 100644 (file)
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini

index eedfe9da765e3e9d73deb0632fecf032dc398fd0..1cf9040137853148ff1adbed15b87ae6c6e4b6a4 100644 (file)
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -267,6 +268,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini

index 11027e0cccafcc94c0485556b62e77e434efb0f5..250783f94811cc645fac0d8286c924a283780b0a 100644 (file)
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -665,6 +666,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini

index 91fb4fb7f0449b36678c92c24f89119bf3272c31..168018c037fad95fafacd05a75eda2f2600b42bc 100644 (file)
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
  eventq_index=0
  init_param=0
  kernel=
+kernel_addr_check=true
  load_addr_mask=1099511627775
  load_offset=0
  mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -603,7 +605,7 @@ env=
  errout=cerr
  euid=100
  eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
  gid=100
  input=cin
  max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini

index 881006e7f82a71f13e4e8564f54e26cedc39534b..31653027e635f817a5a95f891b360d8eabe311b0 100644 (file)
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini

index 896591c78ac97157ee2d1174e328ec19c226247e..b930735f4c779413482c8e4fbb023e92e76c7ac8 100644 (file)
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -234,6 +235,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini

index e7e2c3de4f486e8f003f29e347b9176087ed02af..f2c2bbb5622438f83958cd929ba10e9b5c526cfc 100644 (file)
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -763,6 +764,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr

old mode 100644 (file)

new mode 100755 (executable)
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout

old mode 100644 (file)

new mode 100755 (executable)
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini

index d8488904a212d6f7aa27e6c410847d5804f1918c..963ba125810e0f5af2e05fc88e16bcb9f7b7eb8f 100644 (file)
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
  type=DerivO3CPU
  children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu.fuPool
  function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
  
  [system.cpu.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu.dcache]
  type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
  sequential_access=false
-size=262144
+size=32768
  system=system
  tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu.dcache_port
  mem_side=system.cpu.toL2Bus.slave[1]
  
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
  eventq_index=0
  hit_latency=2
  sequential_access=false
-size=262144
+size=32768
  
  [system.cpu.dstage2_mmu]
  type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
  
  [system.cpu.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
  eventq_index=0
  
  [system.cpu.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu.fuPool.FUList0.opList
  
@@ -249,10 +249,10 @@ opLat=1
  
  [system.cpu.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
  
  [system.cpu.fuPool.FUList1.opList0]
  type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
  [system.cpu.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
  
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
  
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
  
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu.icache]
  type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
-size=131072
+size=32768
  system=system
  tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
-size=131072
+size=32768
  
  [system.cpu.interrupts]
  type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
  
  [system.cpu.l2cache]
  type=BaseCache
-children=tags
+children=prefetcher tags
  addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=20
+hit_latency=12
  is_top_level=false
  max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  system=system
  tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.toL2Bus.master[0]
  mem_side=system.membus.slave[1]
  
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
  [system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=20
+hit_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -712,6 +688,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini

index b37d84887bfb48007a22392356133c23bc575355..52b17d81d69e3c9a3b820c7aa5910d922e253e1a 100644 (file)
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini

index 50fb5bed271f3c822f0d76f71ded89a60257c9fe..0035560c61bcd62dcc8ec9bad15a2384b35ede5f 100644 (file)
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -332,6 +333,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini

index b76f802a94bc78a7557fa7a4fc22c4f9b9b81182..fd6e14d22c855c3cdd5ab8c3622dc49665dbde9e 100644 (file)
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini

index fb7b292e6a96902a433499dc10598147e95327d7..fc5d4f3414292d69b13f20f7f7e8e9950963dcaf 100644 (file)
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -233,6 +234,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini

index c83cd6a89d74f38ad533fb16d05ef467bac787e2..bfaee19bf7f578c703801b833c3df25757eaddc1 100644 (file)
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -614,10 +614,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -647,6 +648,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -687,6 +715,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -700,19 +729,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini

index 6e31ea4d29f9b53c506c42e8bc06394a711fa1fd..26fe45507a4e0a636c7138e48375099616d1f17a 100644 (file)
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini

index 3e9d33bf370b9bb41d5d95e1cc2ce87b2ba78475..4909b25e3a8170a49505dfeb17aef133424a5f1f 100644 (file)
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -267,6 +268,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini

index c53360e80f482ce059063439708c6e2b827715a3..ee9b56ccf599daa49e12bcee07ae2291b5965483 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -84,9 +84,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -217,9 +214,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -393,7 +387,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -474,11 +468,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -539,10 +534,11 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -611,6 +607,7 @@ HeaderType=0
  InterruptLine=30
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1066,6 +1063,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini

index 23c1b6367cf57994f398bc5c2e36678ae9e66377..3f9a7bd5f247265c1feb244bbfbd6c47225a095d 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -84,9 +84,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -224,10 +221,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -306,7 +304,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -352,11 +350,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -478,6 +477,7 @@ HeaderType=0
  InterruptLine=30
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -933,6 +933,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini

index 39f3dd9715d88de522c2a56f68912a8d8bcfd853..f7c4e30f81f48269ca2b566cb078757a9605c456 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -379,7 +379,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -460,11 +460,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -492,8 +493,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -502,6 +528,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -515,19 +542,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -555,10 +589,11 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -627,6 +662,7 @@ HeaderType=0
  InterruptLine=30
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1082,6 +1118,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini

index dfa1ea3555fd96fd9496fed2691aa33e805eb79b..e05c30aba9a53720e41f9b11da37706a12e7e003 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -217,10 +217,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -299,7 +300,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -345,11 +346,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -377,8 +379,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -387,6 +414,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -400,19 +428,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -501,6 +536,7 @@ HeaderType=0
  InterruptLine=30
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -956,6 +992,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini

index 9cd433cc27495071d612b2ac0c826dcc543c2506..2198282f2566a939fbcb1ee13e50c1574e4acc43 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -37,7 +37,7 @@ load_offset=0
  machine_type=RealView_PBX
  mem_mode=atomic
  mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
  multi_proc=true
  num_work_ids=16
  panic_on_oops=true
@@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain
  
  [system.cpu0]
  type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
  branchPred=Null
  checker=Null
  clk_domain=system.cpu_clk_domain
@@ -124,9 +124,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -143,14 +140,14 @@ icache_port=system.cpu0.icache.cpu_side
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
@@ -158,15 +155,15 @@ sequential_access=false
  size=32768
  system=system
  tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu0.toL2Bus.slave[1]
  
  [system.cpu0.dcache.tags]
  type=LRU
-assoc=4
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
@@ -196,7 +193,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[5]
+port=system.cpu0.toL2Bus.slave[5]
  
  [system.cpu0.dtb]
  type=ArmTLB
@@ -213,40 +210,40 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu0.toL2Bus.slave[3]
  
  [system.cpu0.icache]
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
  size=32768
  system=system
  tags=system.cpu0.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu0.toL2Bus.slave[0]
  
  [system.cpu0.icache.tags]
  type=LRU
-assoc=1
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
  size=32768
  
@@ -305,7 +302,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[4]
+port=system.cpu0.toL2Bus.slave[4]
  
  [system.cpu0.itb]
  type=ArmTLB
@@ -322,7 +319,71 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
  
  [system.cpu0.tracer]
  type=ExeTracer
@@ -330,7 +391,7 @@ eventq_index=0
  
  [system.cpu1]
  type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
  branchPred=Null
  checker=Null
  clk_domain=system.cpu_clk_domain
@@ -355,9 +416,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -374,14 +432,14 @@ icache_port=system.cpu1.icache.cpu_side
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
@@ -389,15 +447,15 @@ sequential_access=false
  size=32768
  system=system
  tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[7]
+mem_side=system.cpu1.toL2Bus.slave[1]
  
  [system.cpu1.dcache.tags]
  type=LRU
-assoc=4
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
@@ -427,7 +485,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[11]
+port=system.cpu1.toL2Bus.slave[5]
  
  [system.cpu1.dtb]
  type=ArmTLB
@@ -444,40 +502,40 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[9]
+port=system.cpu1.toL2Bus.slave[3]
  
  [system.cpu1.icache]
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
  size=32768
  system=system
  tags=system.cpu1.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[6]
+mem_side=system.cpu1.toL2Bus.slave[0]
  
  [system.cpu1.icache.tags]
  type=LRU
-assoc=1
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
  size=32768
  
@@ -536,7 +594,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[10]
+port=system.cpu1.toL2Bus.slave[4]
  
  [system.cpu1.itb]
  type=ArmTLB
@@ -553,7 +611,71 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[8]
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
  
  [system.cpu1.tracer]
  type=ExeTracer
@@ -581,13 +703,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -612,7 +734,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -661,11 +783,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -706,12 +829,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -766,6 +889,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -850,6 +974,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
@@ -1168,15 +1302,16 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
  master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
  
  [system.vncserver]
  type=VncServer
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini

index 33ea68a30d81bfea93b4f6a7c7e729a8f68b6778..77c7c4efbc68f195674f1604ccda2bc0942d3c3f 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -124,9 +124,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -360,10 +357,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -396,13 +394,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -427,7 +425,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -441,11 +439,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -486,12 +485,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -546,6 +545,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -630,6 +630,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini

index bfa4aa6e371964ed1783482e0bd02ae4c056aac0..a2ee5f35a3cd68f068f2d89e73a0692d250439c3 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -37,7 +37,7 @@ load_offset=0
  machine_type=RealView_PBX
  mem_mode=timing
  mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
  multi_proc=true
  num_work_ids=16
  panic_on_oops=true
@@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain
  
  [system.cpu0]
  type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
  branchPred=Null
  checker=Null
  clk_domain=system.cpu_clk_domain
@@ -136,14 +136,14 @@ icache_port=system.cpu0.icache.cpu_side
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
@@ -151,15 +151,15 @@ sequential_access=false
  size=32768
  system=system
  tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu0.toL2Bus.slave[1]
  
  [system.cpu0.dcache.tags]
  type=LRU
-assoc=4
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
@@ -189,7 +189,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[5]
+port=system.cpu0.toL2Bus.slave[5]
  
  [system.cpu0.dtb]
  type=ArmTLB
@@ -206,40 +206,40 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu0.toL2Bus.slave[3]
  
  [system.cpu0.icache]
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
  size=32768
  system=system
  tags=system.cpu0.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu0.toL2Bus.slave[0]
  
  [system.cpu0.icache.tags]
  type=LRU
-assoc=1
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
  size=32768
  
@@ -298,7 +298,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[4]
+port=system.cpu0.toL2Bus.slave[4]
  
  [system.cpu0.itb]
  type=ArmTLB
@@ -315,7 +315,71 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
  
  [system.cpu0.tracer]
  type=ExeTracer
@@ -323,7 +387,7 @@ eventq_index=0
  
  [system.cpu1]
  type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
  branchPred=Null
  checker=Null
  clk_domain=system.cpu_clk_domain
@@ -360,14 +424,14 @@ icache_port=system.cpu1.icache.cpu_side
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=4
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
@@ -375,15 +439,15 @@ sequential_access=false
  size=32768
  system=system
  tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[7]
+mem_side=system.cpu1.toL2Bus.slave[1]
  
  [system.cpu1.dcache.tags]
  type=LRU
-assoc=4
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
@@ -413,7 +477,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[11]
+port=system.cpu1.toL2Bus.slave[5]
  
  [system.cpu1.dtb]
  type=ArmTLB
@@ -430,40 +494,40 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[9]
+port=system.cpu1.toL2Bus.slave[3]
  
  [system.cpu1.icache]
  type=BaseCache
  children=tags
  addr_ranges=0:18446744073709551615
-assoc=1
+assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
  size=32768
  system=system
  tags=system.cpu1.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[6]
+mem_side=system.cpu1.toL2Bus.slave[0]
  
  [system.cpu1.icache.tags]
  type=LRU
-assoc=1
+assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
  size=32768
  
@@ -522,7 +586,7 @@ eventq_index=0
  is_stage2=true
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[10]
+port=system.cpu1.toL2Bus.slave[4]
  
  [system.cpu1.itb]
  type=ArmTLB
@@ -539,7 +603,71 @@ eventq_index=0
  is_stage2=false
  num_squash_per_cycle=2
  sys=system
-port=system.toL2Bus.slave[8]
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
  
  [system.cpu1.tracer]
  type=ExeTracer
@@ -567,13 +695,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -598,7 +726,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -647,11 +775,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -679,8 +808,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -689,6 +843,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -702,19 +857,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -722,12 +884,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -782,6 +944,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -866,6 +1029,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
@@ -1184,15 +1357,16 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
  master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
  
  [system.vncserver]
  type=VncServer
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini

index 04e6b79a5e43158f8cc3d1f4215a461a64b287bd..2c07f27f558bd302b088f40eb022ea1a6a5fc169 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -353,10 +353,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -389,13 +390,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -420,7 +421,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -434,11 +435,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -466,8 +468,33 @@ pio=system.membus.default
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -476,6 +503,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -489,19 +517,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
@@ -509,12 +544,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -569,6 +604,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -653,6 +689,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini

index a17b68bb893cf27962a9eaa21e5014ff1ba403fa..3b28bd981bd36730cf9638f742566193e36150db 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -37,7 +37,7 @@ load_offset=0
  machine_type=RealView_PBX
  mem_mode=atomic
  mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
  multi_proc=true
  num_work_ids=16
  panic_on_oops=true
@@ -124,9 +124,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -355,9 +352,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -501,13 +495,13 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
  use_default_range=false
  width=8
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side
  slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
  
  [system.iocache]
@@ -532,7 +526,7 @@ tags=system.iocache.tags
  tgts_per_mshr=12
  two_queue=false
  write_buffers=8
-cpu_side=system.iobus.master[25]
+cpu_side=system.iobus.master[26]
  mem_side=system.membus.slave[2]
  
  [system.iocache.tags]
@@ -581,11 +575,12 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -626,12 +621,12 @@ port=system.membus.master[6]
  
  [system.realview]
  type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
  eventq_index=0
  intrctrl=system.intrctrl
-max_mem_size=268435456
-mem_start_addr=0
  pci_cfg_base=0
+pci_cfg_gen_offsets=false
+pci_io_base=0
  system=system
  
  [system.realview.a9scu]
@@ -686,6 +681,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -770,6 +766,16 @@ pio_latency=100000
  system=system
  pio=system.iobus.master[9]
  
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=268496896
+pio_latency=100000
+system=system
+pio=system.iobus.master[25]
+
  [system.realview.flash_fake]
  type=IsaFake
  clk_domain=system.clk_domain
@@ -1088,10 +1094,11 @@ output=true
  port=3456
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini

index 607c8b43ec0803db5030c33ac25df5b9163aad31..9627624a238ea55fb7c22383a72393d67b3eb84e 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -75,7 +75,7 @@ type=Bridge
  clk_domain=system.clk_domain
  delay=50000
  eventq_index=0
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
  req_size=16
  resp_size=16
  master=system.iobus.slave[0]
@@ -114,9 +114,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -357,10 +354,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -389,8 +387,8 @@ transition_latency=100000000
  
  [system.e820_table]
  type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
  eventq_index=0
  
  [system.e820_table.entries0]
@@ -416,6 +414,13 @@ size=133169152
  
  [system.e820_table.entries3]
  type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
  addr=4294901760
  eventq_index=0
  range_type=2
@@ -464,13 +469,13 @@ version=17
  [system.intel_mp_table.base_entries02]
  type=X86IntelMPBus
  bus_id=0
-bus_type=ISA
+bus_type=PCI
  eventq_index=0
  
  [system.intel_mp_table.base_entries03]
  type=X86IntelMPBus
  bus_id=1
-bus_type=PCI
+bus_type=ISA
  eventq_index=0
  
  [system.intel_mp_table.base_entries04]
@@ -480,7 +485,7 @@ dest_io_apic_intin=16
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
  source_bus_irq=16
  trigger=ConformTrigger
  
@@ -491,7 +496,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=0
  trigger=ConformTrigger
  
@@ -502,7 +507,7 @@ dest_io_apic_intin=2
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=0
  trigger=ConformTrigger
  
@@ -513,7 +518,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=1
  trigger=ConformTrigger
  
@@ -524,7 +529,7 @@ dest_io_apic_intin=1
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=1
  trigger=ConformTrigger
  
@@ -535,7 +540,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=3
  trigger=ConformTrigger
  
@@ -546,7 +551,7 @@ dest_io_apic_intin=3
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=3
  trigger=ConformTrigger
  
@@ -557,7 +562,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=4
  trigger=ConformTrigger
  
@@ -568,7 +573,7 @@ dest_io_apic_intin=4
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=4
  trigger=ConformTrigger
  
@@ -579,7 +584,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=5
  trigger=ConformTrigger
  
@@ -590,7 +595,7 @@ dest_io_apic_intin=5
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=5
  trigger=ConformTrigger
  
@@ -601,7 +606,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=6
  trigger=ConformTrigger
  
@@ -612,7 +617,7 @@ dest_io_apic_intin=6
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=6
  trigger=ConformTrigger
  
@@ -623,7 +628,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=7
  trigger=ConformTrigger
  
@@ -634,7 +639,7 @@ dest_io_apic_intin=7
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=7
  trigger=ConformTrigger
  
@@ -645,7 +650,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=8
  trigger=ConformTrigger
  
@@ -656,7 +661,7 @@ dest_io_apic_intin=8
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=8
  trigger=ConformTrigger
  
@@ -667,7 +672,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=9
  trigger=ConformTrigger
  
@@ -678,7 +683,7 @@ dest_io_apic_intin=9
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=9
  trigger=ConformTrigger
  
@@ -689,7 +694,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=10
  trigger=ConformTrigger
  
@@ -700,7 +705,7 @@ dest_io_apic_intin=10
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=10
  trigger=ConformTrigger
  
@@ -711,7 +716,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=11
  trigger=ConformTrigger
  
@@ -722,7 +727,7 @@ dest_io_apic_intin=11
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=11
  trigger=ConformTrigger
  
@@ -733,7 +738,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=12
  trigger=ConformTrigger
  
@@ -744,7 +749,7 @@ dest_io_apic_intin=12
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=12
  trigger=ConformTrigger
  
@@ -755,7 +760,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=13
  trigger=ConformTrigger
  
@@ -766,7 +771,7 @@ dest_io_apic_intin=13
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=13
  trigger=ConformTrigger
  
@@ -777,7 +782,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=14
  trigger=ConformTrigger
  
@@ -788,15 +793,15 @@ dest_io_apic_intin=14
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=14
  trigger=ConformTrigger
  
  [system.intel_mp_table.ext_entries]
  type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
  eventq_index=0
-parent_bus=1
+parent_bus=0
  subtractive_decode=true
  
  [system.intrctrl]
@@ -805,7 +810,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -851,11 +856,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -1100,6 +1106,7 @@ HeaderType=0
  InterruptLine=14
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=9223372036854775808
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt

index ec6df0068aedf60ffaee5517f44bd98c3477cd22..52d540f15887f4339f0015f6461768d4aa7ba124 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -1,105 +1,105 @@
  
  ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.112127                       # Number of seconds simulated
-sim_ticks                                5112126720000                       # Number of ticks simulated
-final_tick                               5112126720000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.112155                       # Number of seconds simulated
+sim_ticks                                5112155173500                       # Number of ticks simulated
+final_tick                               5112155173500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
  sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1627732                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3332615                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            41616843658                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 647148                       # Number of bytes of host memory used
-host_seconds                                   122.84                       # Real time elapsed on the host
-sim_insts                                   199947158                       # Number of instructions simulated
-sim_ops                                     409371517                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1096092                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2244090                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            28012193632                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 637772                       # Number of bytes of host memory used
+host_seconds                                   182.50                       # Real time elapsed on the host
+sim_insts                                   200033988                       # Number of instructions simulated
+sim_ops                                     409540726                       # Number of ops (including micro ops) simulated
  system.voltage_domain.voltage                       1                       # Voltage in Volts
  system.clk_domain.clock                          1000                       # Clock period in ticks
  system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
  system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
  system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            852352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10669504                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11550592                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       852352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          852352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6285632                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            852288                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10678208                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             11559232                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       852288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          852288                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6294336                       # Number of bytes written to this memory
  system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9275712                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9284416                       # Number of bytes written to this memory
  system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
  system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
  system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              13318                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             166711                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                180478                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           98213                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              13317                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             166847                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                180613                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           98349                       # Number of write requests responded to by this memory
  system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               144933                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               145069                       # Number of write requests responded to by this memory
  system.physmem.bw_read::pc.south_bridge.ide         5546                       # Total read bandwidth from this memory (bytes/s)
  system.physmem.bw_read::cpu.dtb.walker             13                       # Total read bandwidth from this memory (bytes/s)
  system.physmem.bw_read::cpu.itb.walker             63                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               166731                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2087097                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2259449                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          166731                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             166731                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1229553                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       584899                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1814453                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1229553                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       590445                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               166718                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2088788                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2261127                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          166718                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             166718                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1231249                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       584896                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1816145                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1231249                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       590442                       # Total bandwidth to/from this memory (bytes/s)
  system.physmem.bw_total::cpu.dtb.walker            13                       # Total bandwidth to/from this memory (bytes/s)
  system.physmem.bw_total::cpu.itb.walker            63                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              166731                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2087097                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4073902                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq            13903648                       # Transaction distribution
-system.membus.trans_dist::ReadResp           13903648                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13796                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13796                       # Transaction distribution
-system.membus.trans_dist::Writeback             98213                       # Transaction distribution
+system.physmem.bw_total::cpu.inst              166718                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2088788                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4077272                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq            13903768                       # Transaction distribution
+system.membus.trans_dist::ReadResp           13903768                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13911                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13911                       # Transaction distribution
+system.membus.trans_dist::Writeback             98349                       # Transaction distribution
  system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
  system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2521                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            2092                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            134490                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           134485                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2525                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            2096                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            134620                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           134615                       # Transaction distribution
  system.membus.trans_dist::MessageReq             1696                       # Transaction distribution
  system.membus.trans_dist::MessageResp            1696                       # Transaction distribution
  system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3392                       # Packet count per connected master and slave (bytes)
  system.membus.pkt_count_system.apicbridge.master::total         3392                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave     20043728                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave     20044188                       # Packet count per connected master and slave (bytes)
  system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      7698244                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       462901                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total     28204873                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       463315                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total     28205747                       # Packet count per connected master and slave (bytes)
  system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        95256                       # Packet count per connected master and slave (bytes)
  system.membus.pkt_count_system.iocache.mem_side::total        95256                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               28303521                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               28304395                       # Packet count per connected master and slave (bytes)
  system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6784                       # Cumulative packet size per connected master and slave (bytes)
  system.membus.pkt_size_system.apicbridge.master::total         6784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave     10027982                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave     10028212                       # Cumulative packet size per connected master and slave (bytes)
  system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio     15396485                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17807872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43232339                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17825216                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43249913                       # Cumulative packet size per connected master and slave (bytes)
  system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3048192                       # Cumulative packet size per connected master and slave (bytes)
  system.membus.pkt_size_system.iocache.mem_side::total      3048192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                46287315                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                46304889                       # Cumulative packet size per connected master and slave (bytes)
  system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            328402                       # Request fanout histogram
+system.membus.snoop_fanout::samples            328677                       # Request fanout histogram
  system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
  system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
  system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
  system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  328402    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  328677    100.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
  system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              328402                       # Request fanout histogram
+system.membus.snoop_fanout::total              328677                       # Request fanout histogram
  system.iocache.tags.replacements                47573                       # number of replacements
  system.iocache.tags.tagsinuse                0.042448                       # Cycle average of tags in use
  system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
  system.iocache.tags.sampled_refs                47589                       # Sample count of references to valid blocks.
  system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4994846765009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.warmup_cycle         4994875221009                       # Cycle when the warmup percentage was hit.
  system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.042448                       # Average occupied blocks per requestor
  system.iocache.tags.occ_percent::pc.south_bridge.ide     0.002653                       # Average percentage of cache occupancy
  system.iocache.tags.occ_percent::total       0.002653                       # Average percentage of cache occupancy
@@ -151,10 +151,10 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
  system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
  system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
  system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq             10011915                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            10011915                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57577                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              10857                       # Transaction distribution
+system.iobus.trans_dist::ReadReq             10012030                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            10012030                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57692                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              10972                       # Transaction distribution
  system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
  system.iobus.trans_dist::MessageReq              1696                       # Transaction distribution
  system.iobus.trans_dist::MessageResp             1696                       # Transaction distribution
@@ -170,18 +170,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1098                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27352                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27812                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total     20043728                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total     20044188                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95256                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95256                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3392                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3392                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                20142376                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                20142836                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
@@ -194,49 +194,49 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2196                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13676                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13906                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total     10027982                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total     10028212                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027808                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027808                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6784                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6784                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                 13062574                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                 13062804                       # Cumulative packet size per connected master and slave (bytes)
  system.cpu_clk_domain.clock                       500                       # Clock period in ticks
  system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10224257410                       # number of cpu cycles simulated
+system.cpu.numCycles                      10224314318                       # number of cpu cycles simulated
  system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
  system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   199947158                       # Number of instructions committed
-system.cpu.committedOps                     409371517                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             374392167                       # Number of integer alu accesses
+system.cpu.committedInsts                   200033988                       # Number of instructions committed
+system.cpu.committedOps                     409540726                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             374550150                       # Number of integer alu accesses
  system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                     2307997                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     39978602                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    374392167                       # number of integer instructions
+system.cpu.num_func_calls                     2308777                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     39994865                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    374550150                       # number of integer instructions
  system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           682348609                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          323388730                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           682630172                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          323525861                       # number of times the integer registers were written
  system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
  system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            233729759                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           157242019                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      35671209                       # number of memory refs
-system.cpu.num_load_insts                    27243676                       # Number of load instructions
-system.cpu.num_store_insts                    8427533                       # Number of store instructions
-system.cpu.num_idle_cycles               9770491320.524229                       # Number of idle cycles
-system.cpu.num_busy_cycles               453766089.475771                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.044381                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.955619                       # Percentage of idle cycles
-system.cpu.Branches                          43128209                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                175380      0.04%      0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu                 373258577     91.18%     91.22% # Class of executed instruction
-system.cpu.op_class::IntMult                   144442      0.04%     91.26% # Class of executed instruction
-system.cpu.op_class::IntDiv                    122944      0.03%     91.29% # Class of executed instruction
+system.cpu.num_cc_register_reads            233820803                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           157313619                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      35680563                       # number of memory refs
+system.cpu.num_load_insts                    27249389                       # Number of load instructions
+system.cpu.num_store_insts                    8431174                       # Number of store instructions
+system.cpu.num_idle_cycles               9770366809.410368                       # Number of idle cycles
+system.cpu.num_busy_cycles               453947508.589632                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.044399                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.955601                       # Percentage of idle cycles
+system.cpu.Branches                          43145769                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                175400      0.04%      0.04% # Class of executed instruction
+system.cpu.op_class::IntAlu                 373418196     91.18%     91.22% # Class of executed instruction
+system.cpu.op_class::IntMult                   144548      0.04%     91.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                    123054      0.03%     91.29% # Class of executed instruction
  system.cpu.op_class::FloatAdd                       0      0.00%     91.29% # Class of executed instruction
  system.cpu.op_class::FloatCmp                       0      0.00%     91.29% # Class of executed instruction
  system.cpu.op_class::FloatCvt                       0      0.00%     91.29% # Class of executed instruction
@@ -263,54 +263,54 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.29% # Cl
  system.cpu.op_class::SimdFloatMult                  0      0.00%     91.29% # Class of executed instruction
  system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.29% # Class of executed instruction
  system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.29% # Class of executed instruction
-system.cpu.op_class::MemRead                 27243676      6.65%     97.94% # Class of executed instruction
-system.cpu.op_class::MemWrite                 8427533      2.06%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 27249389      6.65%     97.94% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8431174      2.06%    100.00% # Class of executed instruction
  system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
  system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  409372552                       # Class of executed instruction
+system.cpu.op_class::total                  409541761                       # Class of executed instruction
  system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
  system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            791918                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.665021                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           243546972                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            792430                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            307.341938                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      148848615500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.665021                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997393                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997393                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            791952                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.663108                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           243645979                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            792464                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            307.453687                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      148876575500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.663108                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997389                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997389                       # Average percentage of cache occupancy
  system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
  system.cpu.icache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
  system.cpu.icache.tags.age_task_id_blocks_1024::1          134                       # Occupied blocks per task id
  system.cpu.icache.tags.age_task_id_blocks_1024::2          289                       # Occupied blocks per task id
  system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
  system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         245131846                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        245131846                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    243546972                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       243546972                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     243546972                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        243546972                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    243546972                       # number of overall hits
-system.cpu.icache.overall_hits::total       243546972                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       792437                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        792437                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       792437                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         792437                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       792437                       # number of overall misses
-system.cpu.icache.overall_misses::total        792437                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    244339409                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    244339409                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    244339409                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    244339409                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    244339409                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    244339409                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003243                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.003243                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.003243                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.003243                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.003243                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.003243                       # miss rate for overall accesses
+system.cpu.icache.tags.tag_accesses         245230921                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        245230921                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    243645979                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       243645979                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     243645979                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        243645979                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    243645979                       # number of overall hits
+system.cpu.icache.overall_hits::total       243645979                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       792471                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        792471                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       792471                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         792471                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       792471                       # number of overall misses
+system.cpu.icache.overall_misses::total        792471                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    244438450                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244438450                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    244438450                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244438450                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244438450                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244438450                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003242                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.003242                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.003242                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.003242                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.003242                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.003242                       # miss rate for overall accesses
  system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -321,12 +321,12 @@ system.cpu.icache.fast_writes                       0                       # nu
  system.cpu.icache.cache_copies                      0                       # number of cache copies performed
  system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
  system.cpu.itb_walker_cache.tags.replacements         3702                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.026447                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.tagsinuse     3.026453                       # Cycle average of tags in use
  system.cpu.itb_walker_cache.tags.total_refs         7640                       # Total number of references to valid blocks.
  system.cpu.itb_walker_cache.tags.sampled_refs         3715                       # Sample count of references to valid blocks.
  system.cpu.itb_walker_cache.tags.avg_refs     2.056528                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5102112149000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.026447                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.026453                       # Average occupied blocks per requestor
  system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.189153                       # Average percentage of cache occupancy
  system.cpu.itb_walker_cache.tags.occ_percent::total     0.189153                       # Average percentage of cache occupancy
  system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
@@ -376,13 +376,13 @@ system.cpu.itb_walker_cache.cache_copies            0                       # nu
  system.cpu.itb_walker_cache.writebacks::writebacks          802                       # number of writebacks
  system.cpu.itb_walker_cache.writebacks::total          802                       # number of writebacks
  system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements         8177                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.013955                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        12514                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs         8191                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.527774                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5101283486500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.013955                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.replacements         8174                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.013947                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        12516                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs         8188                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.528578                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.013947                       # Average occupied blocks per requestor
  system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.313372                       # Average percentage of cache occupancy
  system.cpu.dtb_walker_cache.tags.occ_percent::total     0.313372                       # Average percentage of cache occupancy
  system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
@@ -390,32 +390,32 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6
  system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
  system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
  system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        53146                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        53146                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12515                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        12515                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12515                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        12515                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12515                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        12515                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9372                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         9372                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9372                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         9372                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9372                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         9372                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21887                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21887                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21887                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21887                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21887                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21887                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.428199                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.428199                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.428199                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.428199                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.428199                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.428199                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.tags.tag_accesses        53153                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        53153                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12517                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        12517                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12517                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        12517                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12517                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        12517                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9373                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         9373                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9373                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         9373                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9373                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         9373                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21890                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        21890                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21890                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        21890                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21890                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        21890                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.428186                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.428186                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.428186                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.428186                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.428186                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.428186                       # miss rate for overall accesses
  system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -424,14 +424,14 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
  system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
  system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         2797                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         2797                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::writebacks         2794                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         2794                       # number of writebacks
  system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1623316                       # number of replacements
+system.cpu.dcache.tags.replacements           1623441                       # number of replacements
  system.cpu.dcache.tags.tagsinuse           511.999462                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20184260                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1623828                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.430048                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            20193263                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1623953                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.434635                       # Average number of references to valid blocks.
  system.cpu.dcache.tags.warmup_cycle           7549500                       # Cycle when the warmup percentage was hit.
  system.cpu.dcache.tags.occ_blocks::cpu.data   511.999462                       # Average occupied blocks per requestor
  system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
@@ -441,48 +441,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          233
  system.cpu.dcache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
  system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
  system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88856245                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88856245                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     12022868                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12022868                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8100233                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8100233                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        58899                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         58899                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      20123101                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20123101                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20182000                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20182000                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       905995                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        905995                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       317045                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       317045                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       403061                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       403061                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1223040                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1223040                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1626101                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1626101                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     12928863                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12928863                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8417278                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8417278                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       461960                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       461960                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21346141                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21346141                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21808101                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21808101                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070075                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.070075                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037666                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037666                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872502                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.872502                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.057296                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.057296                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074564                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074564                       # miss rate for overall accesses
+system.cpu.dcache.tags.tag_accesses          88892882                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88892882                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     12028464                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        12028464                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8103633                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8103633                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        58902                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         58902                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      20132097                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20132097                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20190999                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20190999                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       905998                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        905998                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       317173                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       317173                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       403059                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       403059                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1223171                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1223171                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1626230                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1626230                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     12934462                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12934462                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8420806                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8420806                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       461961                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       461961                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21355268                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21355268                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21817229                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21817229                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070045                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070045                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037665                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037665                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872496                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.872496                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.057277                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.057277                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074539                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074539                       # miss rate for overall accesses
  system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -491,59 +491,59 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
  system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
  system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1536734                       # number of writebacks
-system.cpu.dcache.writebacks::total           1536734                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      1536849                       # number of writebacks
+system.cpu.dcache.writebacks::total           1536849                       # number of writebacks
  system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq       15972635                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      15972635                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13796                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13796                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1540333                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2260                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2260                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       314785                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       314785                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1584874                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32530908                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadReq       15972786                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      15972786                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13911                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13911                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1540445                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2264                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2264                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       314909                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       314909                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1584942                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32531741                       # Packet count per connected master and slave (bytes)
  system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         9962                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        21541                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          34147285                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50715968                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    227701267                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        21540                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          34148185                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50718144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    227716857                       # Cumulative packet size per connected master and slave (bytes)
  system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       344448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       778816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          279540499                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       778688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          279558137                       # Cumulative packet size per connected master and slave (bytes)
  system.cpu.toL2Bus.snoops                       48008                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4020451                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      4020727                       # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::mean        3.011846                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.108195                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.108191                       # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            3972823     98.82%     98.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            3973099     98.82%     98.82% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::4              47628      1.18%    100.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4020451                       # Request fanout histogram
-system.cpu.l2cache.tags.replacements           106060                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64822.097552                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3461863                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           170171                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            20.343437                       # Average number of references to valid blocks.
+system.cpu.toL2Bus.snoop_fanout::total        4020727                       # Request fanout histogram
+system.cpu.l2cache.tags.replacements           106197                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64825.457913                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3461872                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           170308                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            20.327125                       # Average number of references to valid blocks.
  system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 51909.062113                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327                       # Average occupied blocks per requestor
  system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.002479                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.132256                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2490.551712                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.348992                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.792069                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.132278                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2490.291417                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.792099                       # Average percentage of cache occupancy
  system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
  system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.038003                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.159032                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.989107                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.037999                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.159058                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.989158                       # Average percentage of cache occupancy
  system.cpu.l2cache.tags.occ_task_id_blocks::1024        64111                       # Occupied blocks per task id
  system.cpu.l2cache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
  system.cpu.l2cache.tags.age_task_id_blocks_1024::1          261                       # Occupied blocks per task id
@@ -551,88 +551,88 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3498
  system.cpu.l2cache.tags.age_task_id_blocks_1024::3        20716                       # Occupied blocks per task id
  system.cpu.l2cache.tags.age_task_id_blocks_1024::4        39582                       # Occupied blocks per task id
  system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978256                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         32243624                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        32243624                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7334                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses         32246059                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        32246059                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7331                       # number of ReadReq hits
  system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3337                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       779106                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1276189                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2065966                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1540333                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1540333                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       779141                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1276184                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2065993                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1540445                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1540445                       # number of Writeback hits
  system.cpu.l2cache.UpgradeReq_hits::cpu.data           22                       # number of UpgradeReq hits
  system.cpu.l2cache.UpgradeReq_hits::total           22                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       180012                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       180012                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         7334                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       180006                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       180006                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         7331                       # number of demand (read+write) hits
  system.cpu.l2cache.demand_hits::cpu.itb.walker         3337                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       779106                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1456201                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2245978                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         7334                       # number of overall hits
+system.cpu.l2cache.demand_hits::cpu.inst       779141                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1456190                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2245999                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         7331                       # number of overall hits
  system.cpu.l2cache.overall_hits::cpu.itb.walker         3337                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       779106                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1456201                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2245978                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       779141                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1456190                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2245999                       # number of overall hits
  system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
  system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        13318                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        32226                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        45550                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1809                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1809                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       134768                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       134768                       # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        13317                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        32232                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        45555                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1813                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1813                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       134898                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       134898                       # number of ReadExReq misses
  system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
  system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        13318                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       166994                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        180318                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        13317                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       167130                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        180453                       # number of demand (read+write) misses
  system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
  system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        13318                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       166994                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       180318                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7335                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.inst        13317                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       167130                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       180453                       # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7332                       # number of ReadReq accesses(hits+misses)
  system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3342                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       792424                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1308415                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2111516                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1540333                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1540333                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1831                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1831                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       314780                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       314780                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7335                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       792458                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1308416                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2111548                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1540445                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1540445                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1835                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1835                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       314904                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       314904                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7332                       # number of demand (read+write) accesses
  system.cpu.l2cache.demand_accesses::cpu.itb.walker         3342                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       792424                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1623195                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2426296                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7335                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       792458                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1623320                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2426452                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7332                       # number of overall (read+write) accesses
  system.cpu.l2cache.overall_accesses::cpu.itb.walker         3342                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       792424                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1623195                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2426296                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       792458                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1623320                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2426452                       # number of overall (read+write) accesses
  system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000136                       # miss rate for ReadReq accesses
  system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001496                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016807                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.024630                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021572                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.987985                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.987985                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.428134                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.428134                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016805                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.024634                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.021574                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.988011                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.988011                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.428378                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.428378                       # miss rate for ReadExReq accesses
  system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000136                       # miss rate for demand accesses
  system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001496                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016807                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.102880                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.074318                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016805                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.102956                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.074369                       # miss rate for demand accesses
  system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000136                       # miss rate for overall accesses
  system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001496                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016807                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.102880                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.074318                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016805                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.102956                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.074369                       # miss rate for overall accesses
  system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -641,8 +641,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
  system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
  system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        98213                       # number of writebacks
-system.cpu.l2cache.writebacks::total            98213                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        98349                       # number of writebacks
+system.cpu.l2cache.writebacks::total            98349                       # number of writebacks
  system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
  
  ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini

index 59e823df9d3c863480d1ee2b78b1e6ad0a1dcea7..2bc3edd207b10e1344f6d5c31d3ff2e6bf620be5 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -75,7 +75,7 @@ type=Bridge
  clk_domain=system.clk_domain
  delay=50000
  eventq_index=0
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
  req_size=16
  resp_size=16
  master=system.iobus.slave[0]
@@ -350,10 +350,11 @@ sequential_access=false
  size=4194304
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -382,8 +383,8 @@ transition_latency=100000000
  
  [system.e820_table]
  type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
  eventq_index=0
  
  [system.e820_table.entries0]
@@ -409,6 +410,13 @@ size=133169152
  
  [system.e820_table.entries3]
  type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
  addr=4294901760
  eventq_index=0
  range_type=2
@@ -457,13 +465,13 @@ version=17
  [system.intel_mp_table.base_entries02]
  type=X86IntelMPBus
  bus_id=0
-bus_type=ISA
+bus_type=PCI
  eventq_index=0
  
  [system.intel_mp_table.base_entries03]
  type=X86IntelMPBus
  bus_id=1
-bus_type=PCI
+bus_type=ISA
  eventq_index=0
  
  [system.intel_mp_table.base_entries04]
@@ -473,7 +481,7 @@ dest_io_apic_intin=16
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
  source_bus_irq=16
  trigger=ConformTrigger
  
@@ -484,7 +492,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=0
  trigger=ConformTrigger
  
@@ -495,7 +503,7 @@ dest_io_apic_intin=2
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=0
  trigger=ConformTrigger
  
@@ -506,7 +514,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=1
  trigger=ConformTrigger
  
@@ -517,7 +525,7 @@ dest_io_apic_intin=1
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=1
  trigger=ConformTrigger
  
@@ -528,7 +536,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=3
  trigger=ConformTrigger
  
@@ -539,7 +547,7 @@ dest_io_apic_intin=3
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=3
  trigger=ConformTrigger
  
@@ -550,7 +558,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=4
  trigger=ConformTrigger
  
@@ -561,7 +569,7 @@ dest_io_apic_intin=4
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=4
  trigger=ConformTrigger
  
@@ -572,7 +580,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=5
  trigger=ConformTrigger
  
@@ -583,7 +591,7 @@ dest_io_apic_intin=5
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=5
  trigger=ConformTrigger
  
@@ -594,7 +602,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=6
  trigger=ConformTrigger
  
@@ -605,7 +613,7 @@ dest_io_apic_intin=6
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=6
  trigger=ConformTrigger
  
@@ -616,7 +624,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=7
  trigger=ConformTrigger
  
@@ -627,7 +635,7 @@ dest_io_apic_intin=7
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=7
  trigger=ConformTrigger
  
@@ -638,7 +646,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=8
  trigger=ConformTrigger
  
@@ -649,7 +657,7 @@ dest_io_apic_intin=8
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=8
  trigger=ConformTrigger
  
@@ -660,7 +668,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=9
  trigger=ConformTrigger
  
@@ -671,7 +679,7 @@ dest_io_apic_intin=9
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=9
  trigger=ConformTrigger
  
@@ -682,7 +690,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=10
  trigger=ConformTrigger
  
@@ -693,7 +701,7 @@ dest_io_apic_intin=10
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=10
  trigger=ConformTrigger
  
@@ -704,7 +712,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=11
  trigger=ConformTrigger
  
@@ -715,7 +723,7 @@ dest_io_apic_intin=11
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=11
  trigger=ConformTrigger
  
@@ -726,7 +734,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=12
  trigger=ConformTrigger
  
@@ -737,7 +745,7 @@ dest_io_apic_intin=12
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=12
  trigger=ConformTrigger
  
@@ -748,7 +756,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=13
  trigger=ConformTrigger
  
@@ -759,7 +767,7 @@ dest_io_apic_intin=13
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=13
  trigger=ConformTrigger
  
@@ -770,7 +778,7 @@ dest_io_apic_intin=0
  eventq_index=0
  interrupt_type=ExtInt
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=14
  trigger=ConformTrigger
  
@@ -781,15 +789,15 @@ dest_io_apic_intin=14
  eventq_index=0
  interrupt_type=INT
  polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
  source_bus_irq=14
  trigger=ConformTrigger
  
  [system.intel_mp_table.ext_entries]
  type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
  eventq_index=0
-parent_bus=1
+parent_bus=0
  subtractive_decode=true
  
  [system.intrctrl]
@@ -798,7 +806,7 @@ eventq_index=0
  sys=system
  
  [system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -844,11 +852,12 @@ sequential_access=false
  size=1024
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -1093,6 +1102,7 @@ HeaderType=0
  InterruptLine=14
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=9223372036854775808
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1383,8 +1393,33 @@ pio=system.iobus.master[9]
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -1393,6 +1428,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -1406,19 +1442,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

index c82f08e2500b46cfaaf3ad4c5b6b1e5b8dc3fb14..89c62f3e353169efc148bbbd42e3088cf9799231 100644 (file)
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,121 +1,121 @@
  
  ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.192511                       # Number of seconds simulated
-sim_ticks                                5192511044000                       # Number of ticks simulated
-final_tick                               5192511044000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.194411                       # Number of seconds simulated
+sim_ticks                                5194410635000                       # Number of ticks simulated
+final_tick                               5194410635000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
  sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1399863                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2698503                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            56649883486                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 595716                       # Number of bytes of host memory used
-host_seconds                                    91.66                       # Real time elapsed on the host
-sim_insts                                   128310974                       # Number of instructions simulated
-sim_ops                                     247343919                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 693425                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1336696                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            28047460404                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 637768                       # Number of bytes of host memory used
+host_seconds                                   185.20                       # Real time elapsed on the host
+sim_insts                                   128422722                       # Number of instructions simulated
+sim_ops                                     247557000                       # Number of ops (including micro ops) simulated
  system.voltage_domain.voltage                       1                       # Voltage in Volts
  system.clk_domain.clock                          1000                       # Clock period in ticks
  system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
  system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            827456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9076288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9932544                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       827456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          827456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5141952                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            829440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9099264                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9957440                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       829440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          829440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5149824                       # Number of bytes written to this memory
  system.physmem.bytes_written::pc.south_bridge.ide      2990080                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8132032                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8139904                       # Number of bytes written to this memory
  system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
  system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12929                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141817                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                155196                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           80343                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12960                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142176                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                155585                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           80466                       # Number of write requests responded to by this memory
  system.physmem.num_writes::pc.south_bridge.ide        46720                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               127063                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide         5460                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker             25                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               127186                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         5458                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker             12                       # Total read bandwidth from this memory (bytes/s)
  system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               159356                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1747957                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1912859                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          159356                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             159356                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            990263                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       575845                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1566108                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            990263                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       581305                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker            25                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               159679                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1751741                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1916953                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          159679                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             159679                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            991416                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       575634                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1567051                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            991416                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       581092                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker            12                       # Total bandwidth to/from this memory (bytes/s)
  system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              159356                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1747957                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3478967                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        155196                       # Number of read requests accepted
-system.physmem.writeReqs                       127063                       # Number of write requests accepted
-system.physmem.readBursts                      155196                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     127063                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9914944                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     17600                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8130496                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9932544                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8132032                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      275                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst              159679                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1751741                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3484003                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        155585                       # Number of read requests accepted
+system.physmem.writeReqs                       127186                       # Number of write requests accepted
+system.physmem.readBursts                      155585                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     127186                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9942720                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     14720                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8138624                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9957440                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8139904                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      230                       # Number of DRAM read bursts serviced by the write queue
  system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1594                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10479                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9637                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10137                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9789                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9555                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9513                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9351                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                9512                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9073                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8991                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9630                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9438                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9550                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10095                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10146                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10025                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8301                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8002                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8301                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8212                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7990                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7535                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7392                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7734                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7444                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7612                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7970                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7896                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8102                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8416                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8297                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7835                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           1629                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10087                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9924                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10111                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9612                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10046                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9507                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9544                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                9545                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9177                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                9299                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9268                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9485                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9621                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9970                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10158                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10001                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8060                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7801                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7998                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7765                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8116                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7896                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7662                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7717                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7519                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7838                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7675                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7654                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8493                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8626                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8402                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7944                       # Per bank write bursts
  system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
  system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5192510980500                       # Total gap between requests
+system.physmem.totGap                    5194410571500                       # Total gap between requests
  system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
  system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  155196                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  155585                       # Read request sizes (log2)
  system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
  system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 127063                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    151525                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2962                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        63                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        55                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 127186                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    151951                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2969                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        62                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        57                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::4                        34                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
  system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
@@ -159,259 +159,261 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
  system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
  system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
  system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6392                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7445                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8789                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9861                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6417                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      254                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        57292                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      314.972003                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.928814                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.427002                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          21127     36.88%     36.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        13732     23.97%     60.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5729     10.00%     70.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3461      6.04%     76.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2250      3.93%     80.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1575      2.75%     83.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1105      1.93%     85.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1008      1.76%     87.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7305     12.75%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          57292                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5905                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.232854                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      621.882480                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5904     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2364                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6410                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7424                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8845                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9948                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8439                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7452                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6421                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      197                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      186                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        55971                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      323.047292                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     191.702498                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.763320                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19466     34.78%     34.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        13850     24.74%     59.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5737     10.25%     69.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3527      6.30%     76.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2331      4.16%     80.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1635      2.92%     83.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1137      2.03%     85.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          981      1.75%     86.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7307     13.05%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          55971                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5932                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.188806                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      621.686791                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5931     99.98%     99.98% # Reads before turning the bus around for writes
  system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5905                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5905                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.513802                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.393687                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       14.130484                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4886     82.74%     82.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              42      0.71%     83.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              41      0.69%     84.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             275      4.66%     88.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             267      4.52%     93.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              20      0.34%     93.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              10      0.17%     93.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              19      0.32%     94.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              22      0.37%     94.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               8      0.14%     94.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.10%     94.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.03%     94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             226      3.83%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.10%     98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.07%     98.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               3      0.05%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              15      0.25%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              13      0.22%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             6      0.10%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             3      0.05%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             8      0.14%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.03%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             3      0.05%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            12      0.20%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5905                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1558594500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4463363250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    774605000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10060.58                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5932                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5932                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.437289                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.381245                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.855005                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4878     82.23%     82.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              44      0.74%     82.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              36      0.61%     83.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             295      4.97%     88.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             297      5.01%     93.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              20      0.34%     93.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              18      0.30%     94.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              14      0.24%     94.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              21      0.35%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               5      0.08%     94.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.02%     94.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               3      0.05%     94.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             234      3.94%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.05%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.07%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               4      0.07%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               9      0.15%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99              12      0.20%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             5      0.08%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             8      0.13%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             2      0.03%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            10      0.17%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5932                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1472209750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4385116000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    776775000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9476.42                       # Average queueing delay per DRAM burst
  system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28810.58                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28226.42                       # Average memory access latency per DRAM burst
  system.physmem.avgRdBW                           1.91                       # Average DRAM read bandwidth in MiByte/s
  system.physmem.avgWrBW                           1.57                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.91                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.92                       # Average system read bandwidth in MiByte/s
  system.physmem.avgWrBWSys                        1.57                       # Average system write bandwidth in MiByte/s
  system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
  system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
  system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
  system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
  system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.05                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     125976                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     98691                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.32                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18396263.65                       # Average gap between requests
-system.physmem.pageHitRate                      79.67                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     4970934831000                       # Time in different power states
-system.physmem.memoryStateTime::REF      173389320000                       # Time in different power states
+system.physmem.avgWrQLen                        21.88                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     127796                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     98753                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.26                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  77.64                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18369672.18                       # Average gap between requests
+system.physmem.pageHitRate                      80.18                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     4972956663750                       # Time in different power states
+system.physmem.memoryStateTime::REF      173452760000                       # Time in different power states
  system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       48186778000                       # Time in different power states
+system.physmem.memoryStateTime::ACT       48001096250                       # Time in different power states
  system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 214242840                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 218884680                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 116898375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 119431125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                608189400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                600186600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               411266160                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               411946560                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0          339149509920                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1          339149509920                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          134171647065                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          134426407995                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          2997811704000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          2997588229500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            3472483457760                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            3472514596380                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.748507                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.754504                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq              623858                       # Transaction distribution
-system.membus.trans_dist::ReadResp             623858                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13773                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13773                       # Transaction distribution
-system.membus.trans_dist::Writeback             80343                       # Transaction distribution
+system.physmem.actEnergy::0                 211543920                       # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1                 211596840                       # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0                 115425750                       # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1                 115454625                       # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0                611332800                       # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1                600428400                       # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0               408337200                       # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1               415698480                       # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0          339273598560                       # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1          339273598560                       # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0          134393532390                       # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1          134240531850                       # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0          2998756974750                       # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1          2998891185750                       # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0            3473770745370                       # Total energy per rank (pJ)
+system.physmem.totalEnergy::1            3473748494505                       # Total energy per rank (pJ)
+system.physmem.averagePower::0             668.751736                       # Core power per rank (mW)
+system.physmem.averagePower::1             668.747452                       # Core power per rank (mW)
+system.membus.trans_dist::ReadReq              624009                       # Transaction distribution
+system.membus.trans_dist::ReadResp             624009                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13889                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13889                       # Transaction distribution
+system.membus.trans_dist::Writeback             80466                       # Transaction distribution
  system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
  system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2146                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1594                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            113180                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           113180                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1654                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1654                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3308                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3308                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       480328                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710110                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       393589                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1584027                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94722                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        94722                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1682057                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       246444                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420217                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15046144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16712805                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq             2168                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1629                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            113541                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           113541                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1655                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1655                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3310                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3310                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       480788                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710112                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       394547                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1585447                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        94730                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        94730                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1683487                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6620                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6620                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       246674                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420221                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15078912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16745807                       # Cumulative packet size per connected master and slave (bytes)
  system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3018432                       # Cumulative packet size per connected master and slave (bytes)
  system.membus.pkt_size_system.iocache.mem_side::total      3018432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19737853                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              948                       # Total snoops (count)
-system.membus.snoop_fanout::samples            284802                       # Request fanout histogram
+system.membus.pkt_size::total                19770859                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              943                       # Total snoops (count)
+system.membus.snoop_fanout::samples            285344                       # Request fanout histogram
  system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
  system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
  system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
  system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  284802    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  285344    100.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
  system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
  system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              284802                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           256795500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              285344                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           257196000                       # Layer occupancy (ticks)
  system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           358101500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           358105500                       # Layer occupancy (ticks)
  system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3308000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3310000                       # Layer occupancy (ticks)
  system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1310597750                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1311782500                       # Layer occupancy (ticks)
  system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1654000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1655000                       # Layer occupancy (ticks)
  system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2618526656                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2622169871                       # Layer occupancy (ticks)
  system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           54286498                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           54356499                       # Layer occupancy (ticks)
  system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47504                       # number of replacements
-system.iocache.tags.tagsinuse                0.112573                       # Cycle average of tags in use
+system.iocache.tags.replacements                47512                       # number of replacements
+system.iocache.tags.tagsinuse                0.118180                       # Cycle average of tags in use
  system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47520                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47528                       # Sample count of references to valid blocks.
  system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5045778761000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.112573                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007036                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.007036                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5045851318000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.118180                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007386                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.007386                       # Average percentage of cache occupancy
  system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
  system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
  system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428031                       # Number of tag accesses
-system.iocache.tags.data_accesses              428031                       # Number of data accesses
+system.iocache.tags.tag_accesses               428111                       # Number of tag accesses
+system.iocache.tags.data_accesses              428111                       # Number of data accesses
  system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq hits
  system.iocache.WriteInvalidateReq_hits::total        46720                       # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide          839                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              839                       # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          839                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               839                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          839                       # number of overall misses
-system.iocache.overall_misses::total              839                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    140842436                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    140842436                       # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    140842436                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    140842436                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    140842436                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    140842436                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          839                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            839                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          839                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             839                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          839                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            839                       # number of overall (read+write) accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          847                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              847                       # number of ReadReq misses
+system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide            1                       # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total            1                       # number of WriteInvalidateReq misses
+system.iocache.demand_misses::pc.south_bridge.ide          847                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               847                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          847                       # number of overall misses
+system.iocache.overall_misses::total              847                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    141540186                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    141540186                       # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    141540186                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    141540186                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    141540186                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    141540186                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          847                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            847                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46721                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total        46721                       # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide          847                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             847                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          847                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            847                       # number of overall (read+write) accesses
  system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
  system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide     0.000021                       # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total     0.000021                       # miss rate for WriteInvalidateReq accesses
  system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
  system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
  system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
  system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167869.411204                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 167869.411204                       # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167869.411204                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 167869.411204                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167869.411204                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 167869.411204                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 167107.657615                       # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 167107.657615                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 167107.657615                       # average overall miss latency
  system.iocache.blocked_cycles::no_mshrs           471                       # number of cycles access was blocked
  system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.iocache.blocked::no_mshrs                   39                       # number of cycles access was blocked
@@ -420,38 +422,38 @@ system.iocache.avg_blocked_cycles::no_mshrs    12.076923                       #
  system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.iocache.fast_writes                      46720                       # number of fast writes performed
  system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          839                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          839                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          847                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          847                       # number of ReadReq MSHR misses
  system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
  system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          839                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          839                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          839                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          839                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     97188936                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     97188936                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   2836981412                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2836981412                       # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     97188936                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     97188936                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97188936                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     97188936                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          847                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          847                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          847                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          847                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     97471186                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     97471186                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   2827609160                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2827609160                       # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     97471186                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     97471186                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97471186                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     97471186                       # number of overall MSHR miss cycles
  system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
  system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.999979                       # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.999979                       # mshr miss rate for WriteInvalidateReq accesses
  system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
  system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
  system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
  system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 115839.017878                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60723.061045                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60723.061045                       # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 115839.017878                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 115839.017878                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677                       # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60522.456336                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60522.456336                       # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 115078.141677                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 115078.141677                       # average overall mshr miss latency
  system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
  system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
  system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -465,12 +467,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
  system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
  system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
  system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq               230144                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              230144                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57579                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57579                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1654                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1654                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               230267                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              230267                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57693                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57694                       # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq            1                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1655                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1655                       # Transaction distribution
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
@@ -483,18 +486,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio
  system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27236                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27696                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       480328                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95118                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95118                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3308                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3308                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  578754                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       480788                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95134                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95134                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3310                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3310                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  579232                       # Packet count per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
@@ -507,19 +510,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio
  system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13618                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13848                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
  system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       246444                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3280316                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3944816                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total       246674                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027320                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027320                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6620                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6620                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3280614                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3947664                       # Layer occupancy (ticks)
  system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
  system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
  system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -545,7 +548,7 @@ system.iobus.reqLayer11.occupancy              170000                       # La
  system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
  system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            20374000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            20719000                       # Layer occupancy (ticks)
  system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
  system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
@@ -555,47 +558,47 @@ system.iobus.reqLayer16.occupancy                9000                       # La
  system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
  system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           421888846                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           421906845                       # Layer occupancy (ticks)
  system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
  system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
  system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           469469000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           469814000                       # Layer occupancy (ticks)
  system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            52218502                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            52234501                       # Layer occupancy (ticks)
  system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1654000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1655000                       # Layer occupancy (ticks)
  system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
  system.cpu_clk_domain.clock                       500                       # Clock period in ticks
  system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10385022088                       # number of cpu cycles simulated
+system.cpu.numCycles                      10388821270                       # number of cpu cycles simulated
  system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
  system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   128310974                       # Number of instructions committed
-system.cpu.committedOps                     247343919                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             231936467                       # Number of integer alu accesses
+system.cpu.committedInsts                   128422722                       # Number of instructions committed
+system.cpu.committedOps                     247557000                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             232138334                       # Number of integer alu accesses
  system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                     2299885                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     23161985                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    231936467                       # number of integer instructions
+system.cpu.num_func_calls                     2301199                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     23183159                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    232138334                       # number of integer instructions
  system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           434450917                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          197819265                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           434808798                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          197991574                       # number of times the integer registers were written
  system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
  system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            132769519                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            95505601                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      22243286                       # number of memory refs
-system.cpu.num_load_insts                    13879256                       # Number of load instructions
-system.cpu.num_store_insts                    8364030                       # Number of store instructions
-system.cpu.num_idle_cycles               9788400874.998116                       # Number of idle cycles
-system.cpu.num_busy_cycles               596621213.001885                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.057450                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.942550                       # Percentage of idle cycles
-system.cpu.Branches                          26299942                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                174748      0.07%      0.07% # Class of executed instruction
-system.cpu.op_class::IntAlu                 224664535     90.83%     90.90% # Class of executed instruction
-system.cpu.op_class::IntMult                   139903      0.06%     90.96% # Class of executed instruction
-system.cpu.op_class::IntDiv                    122942      0.05%     91.01% # Class of executed instruction
+system.cpu.num_cc_register_reads            132893231                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            95600147                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      22258678                       # number of memory refs
+system.cpu.num_load_insts                    13887993                       # Number of load instructions
+system.cpu.num_store_insts                    8370685                       # Number of store instructions
+system.cpu.num_idle_cycles               9791802498.998116                       # Number of idle cycles
+system.cpu.num_busy_cycles               597018771.001885                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.057467                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.942533                       # Percentage of idle cycles
+system.cpu.Branches                          26323220                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                174807      0.07%      0.07% # Class of executed instruction
+system.cpu.op_class::IntAlu                 224862012     90.83%     90.90% # Class of executed instruction
+system.cpu.op_class::IntMult                   139985      0.06%     90.96% # Class of executed instruction
+system.cpu.op_class::IntDiv                    123095      0.05%     91.01% # Class of executed instruction
  system.cpu.op_class::FloatAdd                       0      0.00%     91.01% # Class of executed instruction
  system.cpu.op_class::FloatCmp                       0      0.00%     91.01% # Class of executed instruction
  system.cpu.op_class::FloatCvt                       0      0.00%     91.01% # Class of executed instruction
@@ -622,66 +625,66 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.01% # Cl
  system.cpu.op_class::SimdFloatMult                  0      0.00%     91.01% # Class of executed instruction
  system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.01% # Class of executed instruction
  system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.01% # Class of executed instruction
-system.cpu.op_class::MemRead                 13879256      5.61%     96.62% # Class of executed instruction
-system.cpu.op_class::MemWrite                 8364030      3.38%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 13887993      5.61%     96.62% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8370685      3.38%    100.00% # Class of executed instruction
  system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
  system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  247345414                       # Class of executed instruction
+system.cpu.op_class::total                  247558577                       # Class of executed instruction
  system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
  system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            790109                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.353605                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           144545821                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            790621                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            182.825679                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      161037022250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.353605                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996784                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996784                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            791372                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.348934                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           144679417                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            791884                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            182.702791                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      161114367250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.348934                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996775                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996775                       # Average percentage of cache occupancy
  system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          297                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          148                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          294                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
  system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146127077                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146127077                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    144545821                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       144545821                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     144545821                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        144545821                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    144545821                       # number of overall hits
-system.cpu.icache.overall_hits::total       144545821                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       790628                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        790628                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       790628                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         790628                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       790628                       # number of overall misses
-system.cpu.icache.overall_misses::total        790628                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11108318120                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11108318120                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11108318120                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11108318120                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11108318120                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11108318120                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    145336449                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    145336449                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    145336449                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    145336449                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    145336449                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    145336449                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005440                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.005440                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.005440                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.005440                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.005440                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.005440                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14049.993322                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14049.993322                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14049.993322                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14049.993322                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14049.993322                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14049.993322                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         146263199                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146263199                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    144679417                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       144679417                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     144679417                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        144679417                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    144679417                       # number of overall hits
+system.cpu.icache.overall_hits::total       144679417                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       791891                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        791891                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       791891                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         791891                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       791891                       # number of overall misses
+system.cpu.icache.overall_misses::total        791891                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11123124618                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11123124618                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11123124618                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11123124618                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11123124618                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11123124618                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    145471308                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    145471308                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    145471308                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    145471308                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    145471308                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    145471308                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005444                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.005444                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.005444                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.005444                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.005444                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.005444                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14046.282403                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14046.282403                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14046.282403                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14046.282403                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14046.282403                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14046.282403                       # average overall miss latency
  system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -690,87 +693,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
  system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.icache.fast_writes                       0                       # number of fast writes performed
  system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       790628                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       790628                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       790628                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       790628                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       790628                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       790628                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9522182380                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   9522182380                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9522182380                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   9522182380                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9522182380                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   9522182380                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005440                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005440                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005440                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.005440                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005440                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.005440                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12043.821342                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12043.821342                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12043.821342                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12043.821342                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12043.821342                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12043.821342                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791891                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       791891                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       791891                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       791891                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       791891                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       791891                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9534445382                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9534445382                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9534445382                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9534445382                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9534445382                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9534445382                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005444                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005444                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005444                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.005444                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005444                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.005444                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12040.098173                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12040.098173                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12040.098173                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12040.098173                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12040.098173                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12040.098173                       # average overall mshr miss latency
  system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements         3485                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.066895                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs         7845                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs         3494                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     2.245278                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5167508806000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.066895                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191681                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.191681                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024            9                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.replacements         3756                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     3.071335                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs         7599                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs         3768                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     2.016720                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5167567118000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.071335                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191958                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.191958                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
  system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.562500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        28811                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        28811                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7868                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         7868                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        29071                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        29071                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7599                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total         7599                       # number of ReadReq hits
  system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
  system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7870                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         7870                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7870                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         7870                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4357                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         4357                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4357                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         4357                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4357                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         4357                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     43584500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total     43584500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     43584500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total     43584500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     43584500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total     43584500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12225                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12225                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7601                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total         7601                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7601                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total         7601                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4623                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         4623                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4623                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         4623                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4623                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         4623                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     47504750                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     47504750                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     47504750                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     47504750                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     47504750                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     47504750                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12222                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        12222                       # number of ReadReq accesses(hits+misses)
  system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
  system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12227                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12227                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12227                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12227                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.356401                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.356401                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.356343                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.356343                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.356343                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.356343                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10003.327978                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10003.327978                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10003.327978                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10003.327978                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10003.327978                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10003.327978                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12224                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        12224                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12224                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        12224                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.378252                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.378252                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.378190                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.378190                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.378190                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.378190                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10275.740861                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10275.740861                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10275.740861                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10275.740861                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10275.740861                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10275.740861                       # average overall miss latency
  system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -779,86 +783,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
  system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
  system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks          747                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total          747                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4357                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4357                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4357                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         4357                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4357                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         4357                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     34868500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     34868500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     34868500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     34868500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     34868500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     34868500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.356401                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.356401                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.356343                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.356343                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.356343                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.356343                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8002.868947                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8002.868947                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8002.868947                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8002.868947                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8002.868947                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8002.868947                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks          825                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          825                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4623                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4623                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4623                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         4623                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4623                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         4623                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     38257250                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     38257250                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     38257250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     38257250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     38257250                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     38257250                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.378252                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.378252                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.378190                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.378190                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.378190                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.378190                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8275.416396                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8275.416396                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8275.416396                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8275.416396                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8275.416396                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8275.416396                       # average overall mshr miss latency
  system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements         7826                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.051872                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        12792                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs         7842                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.631217                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5165211267000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.051872                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315742                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315742                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.replacements         7576                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.056356                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        13259                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs         7591                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.746674                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.056356                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.316022                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.316022                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
  system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
  system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        52641                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        52641                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12792                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        12792                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12792                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        12792                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12792                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        12792                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9019                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         9019                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9019                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         9019                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9019                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         9019                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     95783000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     95783000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     95783000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total     95783000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     95783000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total     95783000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21811                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21811                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21811                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21811                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21811                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21811                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.413507                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.413507                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.413507                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.413507                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.413507                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.413507                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10620.135270                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10620.135270                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10620.135270                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10620.135270                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10620.135270                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10620.135270                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses        52917                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        52917                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13260                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        13260                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13260                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        13260                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13260                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        13260                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8799                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         8799                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8799                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         8799                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8799                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         8799                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     94478000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     94478000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     94478000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total     94478000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     94478000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total     94478000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22059                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        22059                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22059                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        22059                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22059                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        22059                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.398885                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.398885                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.398885                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.398885                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.398885                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.398885                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518                       # average overall miss latency
  system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -867,169 +870,170 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
  system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
  system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         2842                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         2842                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         9019                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         9019                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         9019                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total         9019                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         9019                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total         9019                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     77744500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     77744500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     77744500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     77744500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     77744500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     77744500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.413507                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.413507                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.413507                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.413507                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.413507                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.413507                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8620.079831                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8620.079831                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8620.079831                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8620.079831                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8620.079831                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8620.079831                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks         3010                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         3010                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8799                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8799                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8799                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total         8799                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8799                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total         8799                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     76879500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     76879500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     76879500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     76879500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     76879500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     76879500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.398885                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.398885                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.398885                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.398885                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.398885                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.398885                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8737.299693                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8737.299693                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8737.299693                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8737.299693                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8737.299693                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8737.299693                       # average overall mshr miss latency
  system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1621218                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.996934                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20024389                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1621730                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.347548                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           1622351                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.996907                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            20038370                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1622863                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.347543                       # Average number of references to valid blocks.
  system.cpu.dcache.tags.warmup_cycle          51171250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.996934                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.996907                       # Average occupied blocks per requestor
  system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
  system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
  system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          324                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          338                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
  system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88244906                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88244906                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     11933720                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11933720                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8029176                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8029176                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        59323                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         59323                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      19962896                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19962896                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20022219                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20022219                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       906567                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        906567                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       324536                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       324536                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       402460                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       402460                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1231103                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1231103                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1633563                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1633563                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  12726532750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  12726532750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11379509067                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11379509067                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  24106041817                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  24106041817                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  24106041817                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  24106041817                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12840287                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12840287                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8353712                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8353712                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       461783                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       461783                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21193999                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21193999                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21655782                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21655782                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070603                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.070603                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038849                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.038849                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.871535                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.871535                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.058087                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.058087                       # miss rate for demand accesses
+system.cpu.dcache.tags.tag_accesses          88306374                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88306374                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     11941774                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11941774                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8035174                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8035174                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        59224                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         59224                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      19976948                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19976948                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20036172                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20036172                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       907115                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        907115                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       325077                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       325077                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       402500                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       402500                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1232192                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1232192                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1634692                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1634692                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12725992750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12725992750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  11362158354                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  11362158354                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  24088151104                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  24088151104                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  24088151104                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  24088151104                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12848889                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12848889                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8360251                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8360251                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       461724                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       461724                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21209140                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21209140                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21670864                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21670864                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070599                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070599                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038884                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.038884                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.871733                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.871733                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.058097                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.058097                       # miss rate for demand accesses
  system.cpu.dcache.overall_miss_rate::cpu.data     0.075433                       # miss rate for overall accesses
  system.cpu.dcache.overall_miss_rate::total     0.075433                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.160169                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.160169                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35063.934562                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35063.934562                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19580.848895                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19580.848895                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14756.726136                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14756.726136                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         8324                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19549.024100                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14735.590010                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         7616                       # number of cycles access was blocked
  system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                80                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                81                       # number of cycles access was blocked
  system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   104.050000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    94.024691                       # average number of cycles each access was blocked
  system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
  system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1537872                       # number of writebacks
-system.cpu.dcache.writebacks::total           1537872                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          287                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          287                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9293                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         9293                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         9580                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         9580                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         9580                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         9580                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       906280                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       906280                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315243                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       315243                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402425                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       402425                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1221523                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1221523                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1623948                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1623948                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10906302000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10906302000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10245705379                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10245705379                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5368514000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5368514000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21152007379                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  21152007379                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26520521379                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26520521379                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94214672000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94214672000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2536037000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2536037000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96750709000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  96750709000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070581                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070581                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037737                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037737                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.871459                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.871459                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057635                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.057635                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074989                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.074989                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12034.141766                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12034.141766                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32500.976640                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32500.976640                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13340.408772                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13340.408772                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17316.094236                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17316.094236                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16330.893218                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16330.893218                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1538923                       # number of writebacks
+system.cpu.dcache.writebacks::total           1538923                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          288                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          288                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9252                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         9252                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         9540                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         9540                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         9540                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         9540                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       906827                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       906827                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315825                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       315825                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402464                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402464                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1222652                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1222652                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1625116                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1625116                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10904887500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10904887500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10229869846                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10229869846                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5337291000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5337291000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21134757346                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  21134757346                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26472048346                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26472048346                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94240373000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94240373000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2561690500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2561690500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96802063500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  96802063500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070576                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070576                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037777                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037777                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.871655                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.871655                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057647                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.057647                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074991                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.074991                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482                       # average overall mshr miss latency
  system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
  system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
  system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1037,196 +1041,196 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
  system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
  system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
  system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq        2694994                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2694474                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13773                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13773                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1541461                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        2697012                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2696490                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13889                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13889                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1542758                       # Transaction distribution
  system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46721                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2183                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2183                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       313073                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       313073                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1581243                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5975195                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         7975                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18479                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7582892                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50599360                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203853221                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       231552                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       605440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          255289573                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       53135                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4016986                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        3.011840                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.108164                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2211                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2211                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       313627                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       313627                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1583769                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5979028                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         8638                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18387                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7589822                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50680192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203991823                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       256960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       613632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          255542607                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       52938                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4020768                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        3.011831                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.108123                       # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            3969426     98.82%     98.82% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4              47560      1.18%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            3973200     98.82%     98.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4              47568      1.18%    100.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
  system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4016986                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3830670000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4020768                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     3834027500                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       478500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       487500                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1188381870                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1190285118                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3052447844                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3054401379                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy       6536500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy       6935250                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      13528750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      13198750                       # Layer occupancy (ticks)
  system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements            87289                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64708.241819                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3488268                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           151942                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            22.957892                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            87384                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64746.924059                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3489247                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           152088                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            22.942290                       # Average number of references to valid blocks.
  system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50201.970335                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.012829                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141259                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3236.502324                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11269.615072                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.766021                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50375.433193                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.006760                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141629                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3244.771000                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11126.571476                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.768668                       # Average percentage of cache occupancy
  system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
  system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049385                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.171961                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.987369                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        64653                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           73                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2860                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4737                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56942                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.986526                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         32181921                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        32181921                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6616                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2866                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       777686                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1279269                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2066437                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1541461                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1541461                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          312                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          312                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       199613                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       199613                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         6616                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         2866                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       777686                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1478882                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2266050                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         6616                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         2866                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       777686                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1478882                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2266050                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            2                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049511                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.169778                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.987960                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        64704                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2830                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4041                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        57717                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987305                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         32214708                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        32214708                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6577                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3185                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       778918                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1279822                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2068502                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1542758                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1542758                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          321                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          321                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       199803                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       199803                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         6577                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         3185                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       778918                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1479625                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2268305                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         6577                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         3185                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       778918                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1479625                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2268305                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
  system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12929                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        28637                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        41573                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1319                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1319                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       113455                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       113455                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker            2                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        12960                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        28635                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        41601                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1351                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1351                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       113819                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       113819                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
  system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12929                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       142092                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        155028                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker            2                       # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst        12960                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       142454                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        155420                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
  system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12929                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       142092                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       155028                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       164250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       365000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    954586500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2172547250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3127663000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     15242851                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     15242851                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7899568975                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7899568975                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       164250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       365000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    954586500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10072116225                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11027231975                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       164250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       365000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    954586500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10072116225                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11027231975                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6618                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2871                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       790615                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1307906                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2108010                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1541461                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1541461                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1631                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1631                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       313068                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       313068                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6618                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         2871                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       790615                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1620974                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2421078                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6618                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         2871                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       790615                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1620974                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2421078                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000302                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001742                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016353                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021895                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.019721                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.808706                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.808706                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.362397                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.362397                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000302                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001742                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016353                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.087658                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.064033                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000302                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001742                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016353                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.087658                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.064033                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        82125                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        73000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73832.972388                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75865.043475                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75233.035865                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11556.369219                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11556.369219                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69627.332202                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69627.332202                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        82125                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        73000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73832.972388                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70884.470801                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71130.582701                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        82125                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        73000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73832.972388                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70884.470801                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71130.582701                       # average overall miss latency
+system.cpu.l2cache.overall_misses::cpu.inst        12960                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       142454                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       155420                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker        89250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       350750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    953249250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2133765000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   3087454250                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     15012361                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     15012361                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7880712972                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7880712972                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker        89250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       350750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    953249250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10014477972                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10968167222                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker        89250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       350750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    953249250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10014477972                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10968167222                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6578                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3190                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       791878                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1308457                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2110103                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1542758                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1542758                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1672                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1672                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       313622                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       313622                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6578                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         3190                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       791878                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1622079                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2423725                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6578                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         3190                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       791878                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1622079                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2423725                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000152                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001567                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016366                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021885                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.019715                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.808014                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.808014                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.362918                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.362918                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000152                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001567                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016366                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.087822                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.064124                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000152                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001567                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016366                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.087822                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.064124                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        89250                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        70150                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73553.182870                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74515.976951                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74215.866205                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11112.036269                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11112.036269                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.993244                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.993244                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        89250                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        70150                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73553.182870                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70299.731647                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70571.144138                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        89250                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        70150                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73553.182870                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70299.731647                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70571.144138                       # average overall miss latency
  system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
  system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
  system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1235,90 +1239,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
  system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
  system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
  system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        80343                       # number of writebacks
-system.cpu.l2cache.writebacks::total            80343                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            2                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        80466                       # number of writebacks
+system.cpu.l2cache.writebacks::total            80466                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            1                       # number of ReadReq MSHR misses
  system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12929                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28637                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        41573                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1319                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1319                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113455                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       113455                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            2                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12960                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28635                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        41601                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1351                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1351                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113819                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       113819                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            1                       # number of demand (read+write) MSHR misses
  system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        12929                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       142092                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       155028                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            2                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        12960                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       142454                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       155420                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            1                       # number of overall MSHR misses
  system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        12929                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       142092                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       155028                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       138750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       301500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    792612500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1813424750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2606477500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     13194319                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     13194319                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6481465525                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6481465525                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       138750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       301500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    792612500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8294890275                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9087943025                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       138750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       301500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    792612500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8294890275                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9087943025                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86655868500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86655868500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2370634000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2370634000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89026502500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89026502500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000302                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001742                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016353                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021895                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019721                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.808706                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.808706                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.362397                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.362397                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000302                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001742                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016353                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087658                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.064033                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000302                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001742                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016353                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087658                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.064033                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        69375                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61305.011989                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63324.536439                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62696.401511                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.274450                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.274450                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57128.073025                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57128.073025                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        69375                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61305.011989                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58376.898594                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58621.300830                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        69375                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61305.011989                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58376.898594                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58621.300830                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12960                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       142454                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       155420                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker        76250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       287750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    790892250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1774999000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2566255250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     13524351                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     13524351                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6458128028                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6458128028                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker        76250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       287750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    790892250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8233127028                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9024383278                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker        76250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       287750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    790892250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8233127028                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9024383278                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86680074500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86680074500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2394893500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2394893500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89074968000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89074968000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000152                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001567                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016366                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021885                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019715                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.808014                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.808014                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.362918                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.362918                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000152                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001567                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016366                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087822                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.064124                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000152                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001567                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016366                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087822                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.064124                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        57550                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61025.636574                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61987.043827                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.345256                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.622502                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.622502                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56740.333582                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56740.333582                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        57550                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61025.636574                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57794.986648                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58064.491558                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        76250                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        57550                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61025.636574                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57794.986648                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58064.491558                       # average overall mshr miss latency
  system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
  system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
  system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini

index c8bf9fdf38552c276856b7c0c3e95d3214c95f75..d12ae3672ecc9bec06864fc5b9961a860cd49cca 100644 (file)
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -74,9 +74,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -191,7 +188,7 @@ master=drivesys.membus.slave[3]
  slave=drivesys.iobus.master[29]
  
  [drivesys.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=drivesys.clk_domain
  eventq_index=0
  header_cycles=1
@@ -202,11 +199,12 @@ master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fa
  slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma
  
  [drivesys.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=drivesys.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=drivesys
  use_default_range=false
  width=8
@@ -329,6 +327,7 @@ HeaderType=0
  InterruptLine=30
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -793,6 +792,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1003,9 +1003,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -1120,7 +1117,7 @@ master=testsys.membus.slave[3]
  slave=testsys.iobus.master[29]
  
  [testsys.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=testsys.clk_domain
  eventq_index=0
  header_cycles=1
@@ -1131,11 +1128,12 @@ master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_
  slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
  
  [testsys.membus]
-type=CoherentBus
+type=CoherentXBar
  children=badaddr_responder
  clk_domain=testsys.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=testsys
  use_default_range=false
  width=8
@@ -1258,6 +1256,7 @@ HeaderType=0
  InterruptLine=30
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
@@ -1722,6 +1721,7 @@ HeaderType=0
  InterruptLine=31
  InterruptPin=1
  LatencyTimer=0
+LegacyIOBase=0
  MSICAPBaseOffset=0
  MSICAPCapId=0
  MSICAPMaskBits=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini

index ad6cd67094f240a9f4ff2be6c194763d2a382414..bbd960583a3a0aec7b366036a129f369a4842abe 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -665,6 +666,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini

index 48d1fef7374b89f23cd2a6b91922642ee68edc1e..67de804528b9f4e03f294d381324397750e562a2 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -581,10 +581,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -614,6 +615,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -632,10 +634,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -644,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -654,6 +682,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -667,19 +696,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini

index e3af4adf83dea70808651f68b5dd8c889681cf32..50fa51df76ece1ba3409deb40e6095336459869a 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini

index 1a2ad49164156a99c968667863bfefa316579003..c9e0c15f4e6dc95a1acee722845164ddc159e9ae 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -126,6 +126,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini

index 850afe8f9c970d2a0c6225ee143feb94167baf5c..4de69a578df2f01ea3c5f03f5fb9a926fab94340 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -126,6 +126,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini

index f2c71623d9763291f784964b173ef720922c156f..fe6b478bfb8adfe8b35218c36c758c2d4eef560b 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -126,6 +126,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini

index 07e8d684909495489a7c5365ee60c3348a7d28c9..8663b4c78a93beda00af517358e5b69f2299f29f 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -126,6 +126,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini

index 253b9090368a8d56e267b1251fc85c9622d90017..a87c15412b27d1461d4776c8085a4b7194184a0f 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -126,6 +126,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini

index 0eb5daf95a4cba6628aae6f4723cbf6e5776fed9..091cdad96e9ab08e6751f5d80cc52310847a6a3c 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -234,6 +235,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini

index a68327a1fda9363a11973e918795aa5a29e2be30..c9efff1374f3c810a037adfbd26804c10ca67575 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -665,6 +666,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini

index fb08ec46d595a9f932e113f89a17595d30cffbf5..5f42de6285b44f9849a0cbd1e1104adb03a3a3e9 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -581,10 +581,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -614,6 +615,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -632,10 +634,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -644,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -654,6 +682,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -667,19 +696,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini

index 79159fdc0af1a3dd9c4542313477955863cb50f3..f69c898cbb3bfaae2bd5eb082464a2e2d706a915 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini

index 00c794fb7e21ee68e48b67c6b02752a26ab1c5ce..4519f7012236f1515721005d1b1988c6d95bf74f 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -126,6 +126,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini

index 46d0fbb12bd127bb0956f149b048d35429a7d954..7e18a82efbf7f65ccec724b5e77a9421b422b918 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -126,6 +126,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini

index be173178bfed8c2a32f1a4ea5f0f354d930b0a6d..8de8f1e381a82d26b79a1cf9dc286d5f7be0cdf3 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -126,6 +126,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini

index 1143e388b6870b655ea904bfd9ccca49604aa64c..e617d5b21e0b9c30e725c6ab1a9a9501c5742958 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -126,6 +126,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini

index 670d15d2e284d56342a4588040d10ff3ee6ec890..25deca5e4ad31935e77ca7108953e3de0c18cffb 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -126,6 +126,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini

index 42a4198748b69f4ca95641525bca3480be481bc8..4024427610c7637462944d82eb83c2f2aba2c4e4 100644 (file)
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -234,6 +235,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini

index f4127b6ce22db283579dd659b4e722a95a31d77b..300b9d03534efe470a0476b3f742124e46b42066 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -763,6 +764,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini

index 6c1f6526910b68eab33d226ce91cea8f0bf697ab..78a71faf341c79fc3198df3b9a5e893e003b8d93 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -75,6 +75,7 @@ dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -98,7 +99,7 @@ max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
  numIQEntries=64
-numPhysCCRegs=0
+numPhysCCRegs=1280
  numPhysFloatRegs=256
  numPhysIntRegs=256
  numROBEntries=192
@@ -128,7 +129,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -829,10 +829,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -862,6 +863,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -880,10 +882,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -892,8 +895,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -902,6 +930,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -915,19 +944,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini

index db525069f7fb7f277cbcbd5ae9b27d2b5f3f0aef..a1b6a8304964ff09ab6f9700f8123c94d939edcf 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
  type=DerivO3CPU
  children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
  LFSTSize=1024
-LQEntries=32
+LQEntries=16
  LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
  SSITSize=1024
  activity=0
  backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
  commitWidth=8
  cpu_id=0
  decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
  do_checkpoint_insts=true
  do_quiesce=true
  do_statistics_insts=true
  dstage2_mmu=system.cpu.dstage2_mmu
  dtb=system.cpu.dtb
  eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
  fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
  forwardComSize=5
  fuPool=system.cpu.fuPool
  function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
  max_loads_all_threads=0
  max_loads_any_thread=0
  needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
  numRobs=1
  numThreads=1
  profile=0
  progress_interval=0
  renameToDecodeDelay=1
  renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
  renameToROBDelay=1
-renameWidth=8
+renameWidth=3
  simpoint_start_insts=
  smtCommitPolicy=RoundRobin
  smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
  
  [system.cpu.branchPred]
  type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
  RASSize=16
  choiceCtrBits=2
  choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
  localHistoryTableSize=2048
  localPredictorSize=2048
  numThreads=1
-predType=tournament
+predType=bi-mode
  
  [system.cpu.dcache]
  type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
  hit_latency=2
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=6
  prefetch_on_access=false
  prefetcher=Null
  response_latency=2
  sequential_access=false
-size=262144
+size=32768
  system=system
  tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
-write_buffers=8
+write_buffers=16
  cpu_side=system.cpu.dcache_port
  mem_side=system.cpu.toL2Bus.slave[1]
  
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
  eventq_index=0
  hit_latency=2
  sequential_access=false
-size=262144
+size=32768
  
  [system.cpu.dstage2_mmu]
  type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
  
  [system.cpu.fuPool]
  type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
  eventq_index=0
  
  [system.cpu.fuPool.FUList0]
  type=FUDesc
  children=opList
-count=6
+count=2
  eventq_index=0
  opList=system.cpu.fuPool.FUList0.opList
  
@@ -249,10 +249,10 @@ opLat=1
  
  [system.cpu.fuPool.FUList1]
  type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
  
  [system.cpu.fuPool.FUList1.opList0]
  type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
  [system.cpu.fuPool.FUList1.opList1]
  type=OpDesc
  eventq_index=0
-issueLat=19
+issueLat=12
  opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
  
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
  
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
  eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
  
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=FloatCvt
+opClass=MemRead
  opLat=2
  
  [system.cpu.fuPool.FUList3]
  type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
  children=opList
-count=0
+count=1
  eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
  
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
  
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
  type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
  eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
  
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAdd
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAddAcc
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdAlu
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCmp
-opLat=1
+opLat=4
  
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMult
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdMultAcc
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShift
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdShiftAcc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAdd
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatAlu
-opLat=1
+opLat=5
  
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCmp
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatCvt
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatDiv
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMisc
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMult
-opLat=1
+opLat=3
  
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatMultAcc
  opLat=1
  
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
  type=OpDesc
  eventq_index=0
  issueLat=1
  opClass=SimdFloatSqrt
-opLat=1
+opLat=9
  
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
  
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
  type=OpDesc
  eventq_index=0
  issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
  
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
  type=OpDesc
  eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
  
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
  eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
  
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
  type=OpDesc
  eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
  
  [system.cpu.icache]
  type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=2
+hit_latency=1
  is_top_level=true
  max_miss_count=0
-mshrs=4
+mshrs=2
  prefetch_on_access=false
  prefetcher=Null
-response_latency=2
+response_latency=1
  sequential_access=false
-size=131072
+size=32768
  system=system
  tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=2
+hit_latency=1
  sequential_access=false
-size=131072
+size=32768
  
  [system.cpu.interrupts]
  type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
  
  [system.cpu.l2cache]
  type=BaseCache
-children=tags
+children=prefetcher tags
  addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  forward_snoops=true
-hit_latency=20
+hit_latency=12
  is_top_level=false
  max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  system=system
  tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
  two_queue=false
  write_buffers=8
  cpu_side=system.cpu.toL2Bus.master[0]
  mem_side=system.membus.slave[1]
  
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
  [system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
  block_size=64
  clk_domain=system.cpu_clk_domain
  eventq_index=0
-hit_latency=20
+hit_latency=12
  sequential_access=false
-size=2097152
+size=1048576
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -712,6 +688,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini

index a0f588ff6663c2ca3e02babfef8143db54cd8aff..91da4c557c8248306e07a5b9ef0e80b50016c65e 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -369,6 +366,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -387,10 +385,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini

index d8b9bcc6efd17429cc43ac40e0917919b2173404..2e24c65453aaca107d59aad634292a41be702562 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini

index 017bc1348fcd1dabac6490e650cffe13ddcbf1cc..54668155af9b7780fbe1d8f46c1bec43b1893c80 100644 (file)
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -332,6 +333,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini

index a47df620816c8af6078e6c72dffece0286319d4c..93ee36e3b98c0ac4a33a7373c1fcb05da7190049 100644 (file)
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -237,10 +237,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -270,6 +271,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -288,10 +290,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -300,8 +303,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -310,6 +338,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -323,19 +352,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini

index 1f8305e4efe33fbf267b493407a1759ab3209ea4..946ab8388260b31641c4d893ec9f9d4bf91d963e 100644 (file)
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -583,10 +583,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -616,6 +617,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -634,10 +636,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -646,8 +649,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -656,6 +684,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -669,19 +698,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini

index a20aef42c745c9eabb042d907bf17282d46afa51..4e242dacc7f7f1af0f2d5fb2d601741a6695978b 100644 (file)
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -127,6 +124,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -145,10 +143,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini

index e05997c32670e7937207b295a87a10f31e4c7878..03c7853123bf926ad2b4b17d8c2d5d1e04857f76 100644 (file)
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -128,6 +128,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini

index 1ce9455cf59287c6ee2d6067205341854ba33b4b..e0e01d26c9df4936294bf122dd4b20610515fa69 100644 (file)
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -203,10 +203,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -236,6 +237,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -254,10 +256,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini

index e341fc69a91121b94809844924182a2f11f6920d..709f4f73b01b483a47ca7a685bebcdbab1d52143 100644 (file)
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -75,6 +75,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -127,7 +128,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -581,10 +581,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -614,6 +615,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -632,10 +634,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -644,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -654,6 +682,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -667,19 +696,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini

index 0aa78ac08523629b7d0db39b02058d043f5413f4..00428c3e10853ae6408e293bdf7c69e3cbc61f10 100644 (file)
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -69,9 +69,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini

index facfb2ae6b06bf6f4939bae944ebf9c4e27716f1..a3c44273dee1df7552443c3a9fd1e33b874c9bd6 100644 (file)
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -267,6 +268,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -297,8 +300,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -307,6 +335,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -320,19 +349,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini

index f6abe18a92a275f1df2e54d71b00e8d0c7f5eb59..10cf57bb48c438ff07c1ad4553ca0510701683ea 100644 (file)
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini

index abf61111ca0c421fa4b33b9cbeb50950213afb27..583cc8b930942c70c0a98ed264fad2be60171e73 100644 (file)
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -125,6 +125,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini

index 102ae8d7c1032fe46bdc9457d0876954ab4d6d1e..e38847653edc38089ba26d647cd785abda2adc9f 100644 (file)
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -233,6 +234,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini

index 2be4f154a801eafd4672048e7ad1cde7262bf978..4263ec382a6b94b9b8ec8c68119a1940af4665aa 100644 (file)
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -614,10 +614,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -647,6 +648,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -665,10 +667,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -677,8 +680,33 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -687,6 +715,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -700,19 +729,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini

index db49faad7427705747ce7955296986f1e88d2ae4..960bf1b41f0633f578c9a194813a3df872e594ad 100644 (file)
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -158,6 +155,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -176,10 +174,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini

index 93964b6e78446ae54774e06a47ba92740beeacab..cf742c468a39aacb4c4c5b796caf57a6412992ad 100644 (file)
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -159,6 +159,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.dvfs_handler]
  type=DVFSHandler
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini

index a819aa85995e1dd6c3adf6efeaa47311c4a92e74..5b07510f029167d67faf206423f1a04d0f3ef9d3 100644 (file)
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -267,6 +268,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini

index d285317886694e3a4ed4285ff195852f114bdd61..d358e4bd4f61815a69a9ac4d133133b445b74d33 100644 (file)
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload0 system.cpu.workload1
  dcache_port=system.cpu.dcache.cpu_side
@@ -586,10 +586,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -619,6 +620,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu.workload1]
  type=LiveProcess
@@ -639,6 +641,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -657,10 +660,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -669,8 +673,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -679,6 +708,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -692,19 +722,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini

index d6d7e175a8d702b4fd3debc7fdb4fea64b6cb4ec..c6b990bda32a5a71b842061e07342359df2ac7cd 100644 (file)
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
@@ -234,10 +234,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -267,6 +268,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -285,10 +287,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -297,8 +300,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -307,6 +335,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -320,19 +349,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini

index 2560e1b902ea9fa409d8786893194dd9708cdb34..144f058d7a9b6feee0e544840e581fc1d4372823 100644 (file)
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu.workload
  dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +580,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -613,6 +614,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -631,10 +633,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -643,8 +646,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -653,6 +681,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -666,19 +695,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini

index a0349a47c46cbf5f6308b95e5f4fcfc13ff6d6cc..fc4381d3d056d3d2dd88c20500be34f92346b88e 100644 (file)
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini

index 0cf6b950c921d116bb64730cb75d5b0ee4476bb0..727287e35b3a34b5bfe209f4b0b59c49c5b3bc07 100644 (file)
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
  size=2097152
  
  [system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=32
@@ -233,6 +234,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu_clk_domain]
  type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini

index ea05b957749d1b9a873b2fa19cf31ae97446f244..144007094da08f7bbdf83bbb35bca2e0288ce2bf 100644 (file)
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -74,6 +74,7 @@ do_statistics_insts=true
  dtb=system.cpu0.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -126,7 +127,6 @@ switched_out=false
  system=system
  tracer=system.cpu0.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu0.workload
  dcache_port=system.cpu0.dcache.cpu_side
@@ -567,6 +567,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu1]
  type=DerivO3CPU
@@ -599,6 +600,7 @@ do_statistics_insts=true
  dtb=system.cpu1.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -651,7 +653,6 @@ switched_out=false
  system=system
  tracer=system.cpu1.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu0.workload
  dcache_port=system.cpu1.dcache.cpu_side
@@ -1104,6 +1105,7 @@ do_statistics_insts=true
  dtb=system.cpu2.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -1156,7 +1158,6 @@ switched_out=false
  system=system
  tracer=system.cpu2.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu0.workload
  dcache_port=system.cpu2.dcache.cpu_side
@@ -1609,6 +1610,7 @@ do_statistics_insts=true
  dtb=system.cpu3.dtb
  eventq_index=0
  fetchBufferSize=64
+fetchQueueSize=32
  fetchToDecodeDelay=1
  fetchTrapLatency=1
  fetchWidth=8
@@ -1661,7 +1663,6 @@ switched_out=false
  system=system
  tracer=system.cpu3.tracer
  trapLatency=13
-wbDepth=1
  wbWidth=8
  workload=system.cpu0.workload
  dcache_port=system.cpu3.dcache.cpu_side
@@ -2135,10 +2136,11 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -2147,8 +2149,33 @@ slave=system.system_port system.l2c.mem_side
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -2157,6 +2184,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -2170,29 +2198,37 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
  port=system.membus.master[0]
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout

index 33ff09cf3c5cf3ac7aec2c00f42dd7b04dd7fbf8..90080e4d5c81b16db215745bfc957c1e999a5293 100755 (executable)
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp
  gem5 Simulator System.  http://gem5.org
  gem5 is copyrighted software; use the --copyright option for details.
  
-gem5 compiled Jun 21 2014 11:07:38
-gem5 started Jun 21 2014 11:08:21
-gem5 executing on phenom
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+gem5 compiled Oct 11 2014 05:01:31
+gem5 started Oct 11 2014 05:01:48
+gem5 executing on ribera.cs.wisc.edu
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
  Global frequency set at 1000000000000 ticks per second
  info: Entering event queue @ 0.  Starting simulation...
  Init done
@@ -17,54 +17,54 @@ Init done
  [Iteration 1, Thread 3] Got lock
  [Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
  Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
  [Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
  [Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
  Iteration 2 completed
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
  [Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
  [Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
  Iteration 3 completed
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
  [Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
  Iteration 4 completed
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
  [Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
  [Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
  Iteration 5 completed
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
  [Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
  [Iteration 6, Thread 1] Got lock
  [Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
  Iteration 6 completed
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
  [Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
  Iteration 7 completed
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
  [Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
  [Iteration 8, Thread 3] Got lock
  [Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
  Iteration 8 completed
  [Iteration 9, Thread 3] Got lock
  [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
@@ -75,10 +75,10 @@ Iteration 8 completed
  Iteration 9 completed
  [Iteration 10, Thread 1] Got lock
  [Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
  [Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
  Iteration 10 completed
  PASSED :-)
-Exiting @ tick 110970500 because target called exit()
+Exiting @ tick 105696000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini

index 742ce1ca70bdfe524fc7e8884db1213e9b81d7fe..dc830ef72cba141f7c2d4a5c64069ef74acb6854 100644 (file)
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -194,6 +191,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu1]
  type=AtomicSimpleCPU
@@ -220,9 +218,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -352,9 +347,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -484,9 +476,6 @@ max_loads_any_thread=0
  numThreads=1
  profile=0
  progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
  simpoint_start_insts=
  simulate_data_stalls=false
  simulate_inst_stalls=false
@@ -643,10 +632,11 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -667,10 +657,11 @@ range=0:134217727
  port=system.membus.master[0]
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout

index 79edf97610480e506bbcb3c3e757cf057237a9f3..17be690b9da2a1ab9ecfd016b4cea40cf1be0bb5 100755 (executable)
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
  gem5 Simulator System.  http://gem5.org
  gem5 is copyrighted software; use the --copyright option for details.
  
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 17:29:52
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+gem5 compiled Oct 11 2014 05:01:31
+gem5 started Oct 11 2014 05:01:48
+gem5 executing on ribera.cs.wisc.edu
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
  Global frequency set at 1000000000000 ticks per second
  info: Entering event queue @ 0.  Starting simulation...
  Init done
@@ -29,54 +31,54 @@ Iteration 2 completed
  [Iteration 3, Thread 1] Got lock
  [Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
  Iteration 3 completed
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
  [Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
  [Iteration 4, Thread 1] Got lock
  [Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
  Iteration 4 completed
  [Iteration 5, Thread 3] Got lock
  [Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
  [Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
  Iteration 5 completed
  [Iteration 6, Thread 2] Got lock
  [Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
  [Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
  Iteration 6 completed
  [Iteration 7, Thread 2] Got lock
  [Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
  [Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
  Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
  [Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
  [Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
  Iteration 8 completed
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
  [Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
  [Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
  Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
  [Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
  Iteration 10 completed
  PASSED :-)
  Exiting @ tick 87707000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini

index d83d155aedf3675157db324ba8bc178087520a3f..2ad22e9200a817d4d8a0bbd86610ff250bf2b332 100644 (file)
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -187,6 +187,7 @@ ppid=99
  simpoint=0
  system=system
  uid=100
+useArchPT=false
  
  [system.cpu1]
  type=TimingSimpleCPU
@@ -615,10 +616,11 @@ sequential_access=false
  size=4194304
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
@@ -639,10 +641,11 @@ range=0:134217727
  port=system.membus.master[0]
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=8
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini

index 1c907dde74283288d015f4064c8db40d8f110c9c..58228c89a5a23226e7e25fc18ab6a57e7d25ea04 100644 (file)
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000
  
  [system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr

index b779cf15d4ea42858393e8dbaf71e209dd3e308f..215e9ea821b04ee7d7ddc4d171b4988fa3395aaa 100755 (executable)
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
      0.072760 rounded to 0
  warn: rounding error > tolerance
      0.072760 rounded to 0
-system.cpu7: completed 10000 read, 5432 write accesses @720734
-system.cpu0: completed 10000 read, 5512 write accesses @730548
-system.cpu1: completed 10000 read, 5469 write accesses @733316
-system.cpu3: completed 10000 read, 5348 write accesses @734089
-system.cpu5: completed 10000 read, 5304 write accesses @739554
-system.cpu4: completed 10000 read, 5523 write accesses @742146
-system.cpu2: completed 10000 read, 5353 write accesses @742448
-system.cpu6: completed 10000 read, 5456 write accesses @746526
-system.cpu0: completed 20000 read, 10918 write accesses @1452216
-system.cpu7: completed 20000 read, 10905 write accesses @1455831
-system.cpu2: completed 20000 read, 10616 write accesses @1456643
-system.cpu1: completed 20000 read, 10900 write accesses @1468694
-system.cpu3: completed 20000 read, 10595 write accesses @1471954
-system.cpu6: completed 20000 read, 10732 write accesses @1476612
-system.cpu5: completed 20000 read, 10777 write accesses @1484015
-system.cpu4: completed 20000 read, 10962 write accesses @1484193
-system.cpu7: completed 30000 read, 16301 write accesses @2190709
-system.cpu3: completed 30000 read, 15930 write accesses @2193108
-system.cpu0: completed 30000 read, 16492 write accesses @2204699
-system.cpu2: completed 30000 read, 16137 write accesses @2208852
-system.cpu1: completed 30000 read, 16294 write accesses @2211342
-system.cpu6: completed 30000 read, 16138 write accesses @2217558
-system.cpu5: completed 30000 read, 16017 write accesses @2217893
-system.cpu4: completed 30000 read, 16364 write accesses @2220770
-system.cpu7: completed 40000 read, 21683 write accesses @2923239
-system.cpu3: completed 40000 read, 21410 write accesses @2936019
-system.cpu2: completed 40000 read, 21422 write accesses @2936262
-system.cpu0: completed 40000 read, 21993 write accesses @2938221
-system.cpu5: completed 40000 read, 21407 write accesses @2949381
-system.cpu4: completed 40000 read, 21696 write accesses @2954856
-system.cpu6: completed 40000 read, 21664 write accesses @2955212
-system.cpu1: completed 40000 read, 21772 write accesses @2957373
-system.cpu7: completed 50000 read, 26880 write accesses @3637356
-system.cpu0: completed 50000 read, 27433 write accesses @3667809
-system.cpu2: completed 50000 read, 26841 write accesses @3676541
-system.cpu3: completed 50000 read, 26846 write accesses @3676934
-system.cpu1: completed 50000 read, 27155 write accesses @3679587
-system.cpu5: completed 50000 read, 26712 write accesses @3699925
-system.cpu4: completed 50000 read, 27199 write accesses @3700680
-system.cpu6: completed 50000 read, 27119 write accesses @3709288
-system.cpu7: completed 60000 read, 32133 write accesses @4356266
-system.cpu0: completed 60000 read, 32774 write accesses @4396377
-system.cpu3: completed 60000 read, 32241 write accesses @4405248
-system.cpu2: completed 60000 read, 32179 write accesses @4410455
-system.cpu1: completed 60000 read, 32548 write accesses @4418337
-system.cpu4: completed 60000 read, 32496 write accesses @4444142
-system.cpu6: completed 60000 read, 32520 write accesses @4446125
-system.cpu5: completed 60000 read, 32111 write accesses @4457785
-system.cpu7: completed 70000 read, 37528 write accesses @5092190
-system.cpu3: completed 70000 read, 37618 write accesses @5124227
-system.cpu0: completed 70000 read, 38140 write accesses @5138553
-system.cpu2: completed 70000 read, 37630 write accesses @5148204
-system.cpu4: completed 70000 read, 37860 write accesses @5162780
-system.cpu1: completed 70000 read, 37968 write accesses @5169201
-system.cpu6: completed 70000 read, 38023 write accesses @5190771
-system.cpu5: completed 70000 read, 37447 write accesses @5193894
-system.cpu7: completed 80000 read, 42859 write accesses @5808723
-system.cpu3: completed 80000 read, 43086 write accesses @5863853
-system.cpu2: completed 80000 read, 43034 write accesses @5892131
-system.cpu0: completed 80000 read, 43586 write accesses @5894007
-system.cpu4: completed 80000 read, 43221 write accesses @5909816
-system.cpu1: completed 80000 read, 43381 write accesses @5910301
-system.cpu6: completed 80000 read, 43445 write accesses @5922153
-system.cpu5: completed 80000 read, 42916 write accesses @5926434
-system.cpu7: completed 90000 read, 48423 write accesses @6537227
-system.cpu3: completed 90000 read, 48562 write accesses @6619736
-system.cpu0: completed 90000 read, 48962 write accesses @6625530
-system.cpu2: completed 90000 read, 48441 write accesses @6629626
-system.cpu1: completed 90000 read, 48846 write accesses @6644848
-system.cpu6: completed 90000 read, 48899 write accesses @6650109
-system.cpu4: completed 90000 read, 48617 write accesses @6655860
-system.cpu5: completed 90000 read, 48309 write accesses @6656682
-system.cpu7: completed 100000 read, 53646 write accesses @7259586
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+system.cpu2: completed 10000 read, 5361 write accesses @731568
+system.cpu5: completed 10000 read, 5557 write accesses @735340
+system.cpu3: completed 10000 read, 5535 write accesses @738863
+system.cpu6: completed 10000 read, 5476 write accesses @748316
+system.cpu0: completed 10000 read, 5560 write accesses @752250
+system.cpu4: completed 10000 read, 5465 write accesses @757289
+system.cpu7: completed 10000 read, 5564 write accesses @760144
+system.cpu1: completed 10000 read, 5530 write accesses @768416
+system.cpu5: completed 20000 read, 11151 write accesses @1477095
+system.cpu2: completed 20000 read, 10827 write accesses @1478088
+system.cpu3: completed 20000 read, 11078 write accesses @1481757
+system.cpu0: completed 20000 read, 11117 write accesses @1493889
+system.cpu6: completed 20000 read, 11080 write accesses @1512346
+system.cpu1: completed 20000 read, 11091 write accesses @1512763
+system.cpu4: completed 20000 read, 10986 write accesses @1520589
+system.cpu7: completed 20000 read, 11078 write accesses @1523748
+system.cpu5: completed 30000 read, 16568 write accesses @2200051
+system.cpu3: completed 30000 read, 16616 write accesses @2221845
+system.cpu2: completed 30000 read, 16217 write accesses @2232672
+system.cpu0: completed 30000 read, 16692 write accesses @2249618
+system.cpu1: completed 30000 read, 16648 write accesses @2263101
+system.cpu6: completed 30000 read, 16745 write accesses @2274150
+system.cpu4: completed 30000 read, 16620 write accesses @2276386
+system.cpu7: completed 30000 read, 16733 write accesses @2277359
+system.cpu5: completed 40000 read, 21987 write accesses @2947352
+system.cpu3: completed 40000 read, 22027 write accesses @2968674
+system.cpu1: completed 40000 read, 22148 write accesses @2995890
+system.cpu0: completed 40000 read, 22166 write accesses @2998152
+system.cpu2: completed 40000 read, 21828 write accesses @3001342
+system.cpu7: completed 40000 read, 22152 write accesses @3022463
+system.cpu6: completed 40000 read, 22388 write accesses @3028895
+system.cpu4: completed 40000 read, 22197 write accesses @3031091
+system.cpu5: completed 50000 read, 27444 write accesses @3696748
+system.cpu3: completed 50000 read, 27708 write accesses @3723471
+system.cpu1: completed 50000 read, 27649 write accesses @3746058
+system.cpu0: completed 50000 read, 27719 write accesses @3747410
+system.cpu2: completed 50000 read, 27424 write accesses @3760076
+system.cpu7: completed 50000 read, 27568 write accesses @3771426
+system.cpu6: completed 50000 read, 28012 write accesses @3777023
+system.cpu4: completed 50000 read, 27741 write accesses @3802071
+system.cpu5: completed 60000 read, 33062 write accesses @4446684
+system.cpu3: completed 60000 read, 33331 write accesses @4487796
+system.cpu2: completed 60000 read, 33035 write accesses @4498626
+system.cpu0: completed 60000 read, 33211 write accesses @4505229
+system.cpu1: completed 60000 read, 33219 write accesses @4525223
+system.cpu6: completed 60000 read, 33545 write accesses @4528416
+system.cpu7: completed 60000 read, 33210 write accesses @4528425
+system.cpu4: completed 60000 read, 33325 write accesses @4560641
+system.cpu5: completed 70000 read, 38698 write accesses @5188287
+system.cpu2: completed 70000 read, 38579 write accesses @5235379
+system.cpu7: completed 70000 read, 38633 write accesses @5255909
+system.cpu0: completed 70000 read, 38682 write accesses @5255973
+system.cpu6: completed 70000 read, 38964 write accesses @5261147
+system.cpu3: completed 70000 read, 38993 write accesses @5267174
+system.cpu1: completed 70000 read, 38888 write accesses @5283161
+system.cpu4: completed 70000 read, 38789 write accesses @5300670
+system.cpu5: completed 80000 read, 44039 write accesses @5937946
+system.cpu2: completed 80000 read, 43995 write accesses @5990383
+system.cpu7: completed 80000 read, 44179 write accesses @5992827
+system.cpu0: completed 80000 read, 44154 write accesses @6000956
+system.cpu6: completed 80000 read, 44514 write accesses @6013988
+system.cpu3: completed 80000 read, 44595 write accesses @6025710
+system.cpu1: completed 80000 read, 44663 write accesses @6042332
+system.cpu4: completed 80000 read, 44390 write accesses @6048987
+system.cpu5: completed 90000 read, 49553 write accesses @6694237
+system.cpu7: completed 90000 read, 49635 write accesses @6734659
+system.cpu2: completed 90000 read, 49508 write accesses @6735285
+system.cpu0: completed 90000 read, 49652 write accesses @6748849
+system.cpu6: completed 90000 read, 50083 write accesses @6767267
+system.cpu1: completed 90000 read, 50078 write accesses @6778899
+system.cpu3: completed 90000 read, 50108 write accesses @6783497
+system.cpu4: completed 90000 read, 50077 write accesses @6811616
+system.cpu5: completed 100000 read, 55112 write accesses @7430292
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini

index cce9b7e466ae093fbd82643b642ba0d7e0d7d25c..a6cce7aa1634a909424161e6e371f714072c45f0 100644 (file)
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000
  
  [system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr

index 96061ea3822a9cddc6d82773485e42ed67ae9c14..327665b25011eaad521824036a71e7377beb67b2 100755 (executable)
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
      0.072760 rounded to 0
  warn: rounding error > tolerance
      0.072760 rounded to 0
-system.cpu6: completed 10000 read, 5376 write accesses @740514
-system.cpu0: completed 10000 read, 5364 write accesses @745186
-system.cpu3: completed 10000 read, 5423 write accesses @748707
-system.cpu4: completed 10000 read, 5537 write accesses @749784
-system.cpu7: completed 10000 read, 5400 write accesses @749868
-system.cpu1: completed 10000 read, 5530 write accesses @750998
-system.cpu5: completed 10000 read, 5459 write accesses @756529
-system.cpu2: completed 10000 read, 5543 write accesses @771097
-system.cpu6: completed 20000 read, 10651 write accesses @1479754
-system.cpu3: completed 20000 read, 10879 write accesses @1495041
-system.cpu7: completed 20000 read, 10760 write accesses @1499008
-system.cpu1: completed 20000 read, 10977 write accesses @1499104
-system.cpu5: completed 20000 read, 10867 write accesses @1505086
-system.cpu0: completed 20000 read, 10799 write accesses @1507389
-system.cpu4: completed 20000 read, 11068 write accesses @1508085
-system.cpu2: completed 20000 read, 10878 write accesses @1527233
-system.cpu6: completed 30000 read, 16119 write accesses @2225328
-system.cpu3: completed 30000 read, 16305 write accesses @2244855
-system.cpu5: completed 30000 read, 16187 write accesses @2247278
-system.cpu7: completed 30000 read, 16155 write accesses @2249487
-system.cpu1: completed 30000 read, 16466 write accesses @2250992
-system.cpu0: completed 30000 read, 16273 write accesses @2255206
-system.cpu4: completed 30000 read, 16428 write accesses @2263136
-system.cpu2: completed 30000 read, 16197 write accesses @2278056
-system.cpu6: completed 40000 read, 21573 write accesses @2978557
-system.cpu7: completed 40000 read, 21410 write accesses @2982935
-system.cpu4: completed 40000 read, 21729 write accesses @2999959
-system.cpu3: completed 40000 read, 21781 write accesses @3000904
-system.cpu1: completed 40000 read, 21951 write accesses @3003109
-system.cpu5: completed 40000 read, 21639 write accesses @3013039
-system.cpu0: completed 40000 read, 21607 write accesses @3015250
-system.cpu2: completed 40000 read, 21696 write accesses @3037769
-system.cpu6: completed 50000 read, 26913 write accesses @3719593
-system.cpu7: completed 50000 read, 26968 write accesses @3753645
-system.cpu4: completed 50000 read, 27060 write accesses @3754051
-system.cpu1: completed 50000 read, 27365 write accesses @3755861
-system.cpu0: completed 50000 read, 27035 write accesses @3755945
-system.cpu3: completed 50000 read, 27265 write accesses @3757400
-system.cpu5: completed 50000 read, 27001 write accesses @3763589
-system.cpu2: completed 50000 read, 27364 write accesses @3806785
-system.cpu6: completed 60000 read, 32204 write accesses @4458868
-system.cpu1: completed 60000 read, 32673 write accesses @4480776
-system.cpu0: completed 60000 read, 32481 write accesses @4498229
-system.cpu7: completed 60000 read, 32335 write accesses @4506920
-system.cpu3: completed 60000 read, 32750 write accesses @4507998
-system.cpu4: completed 60000 read, 32435 write accesses @4514030
-system.cpu5: completed 60000 read, 32505 write accesses @4516999
-system.cpu2: completed 60000 read, 32812 write accesses @4572908
-system.cpu6: completed 70000 read, 37702 write accesses @5219683
-system.cpu0: completed 70000 read, 38094 write accesses @5237731
-system.cpu1: completed 70000 read, 38271 write accesses @5247271
-system.cpu5: completed 70000 read, 37826 write accesses @5260789
-system.cpu3: completed 70000 read, 38167 write accesses @5262755
-system.cpu4: completed 70000 read, 37927 write accesses @5268995
-system.cpu7: completed 70000 read, 37729 write accesses @5271169
-system.cpu2: completed 70000 read, 38312 write accesses @5320578
-system.cpu6: completed 80000 read, 43265 write accesses @5963960
-system.cpu0: completed 80000 read, 43558 write accesses @5996302
-system.cpu5: completed 80000 read, 43163 write accesses @6000784
-system.cpu3: completed 80000 read, 43563 write accesses @6009019
-system.cpu1: completed 80000 read, 43846 write accesses @6010830
-system.cpu4: completed 80000 read, 43375 write accesses @6021719
-system.cpu7: completed 80000 read, 43151 write accesses @6032005
-system.cpu2: completed 80000 read, 43642 write accesses @6070842
-system.cpu6: completed 90000 read, 48756 write accesses @6719511
-system.cpu5: completed 90000 read, 48675 write accesses @6752879
-system.cpu0: completed 90000 read, 49075 write accesses @6759943
-system.cpu4: completed 90000 read, 48792 write accesses @6772472
-system.cpu1: completed 90000 read, 49329 write accesses @6774290
-system.cpu3: completed 90000 read, 49090 write accesses @6783540
-system.cpu7: completed 90000 read, 48766 write accesses @6785808
-system.cpu2: completed 90000 read, 49113 write accesses @6821790
-system.cpu6: completed 100000 read, 54332 write accesses @7481441
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+system.cpu6: completed 10000 read, 5503 write accesses @757269
+system.cpu4: completed 10000 read, 5478 write accesses @761080
+system.cpu2: completed 10000 read, 5550 write accesses @763319
+system.cpu1: completed 10000 read, 5614 write accesses @768345
+system.cpu0: completed 10000 read, 5587 write accesses @769447
+system.cpu7: completed 10000 read, 5757 write accesses @772728
+system.cpu5: completed 10000 read, 5702 write accesses @774176
+system.cpu3: completed 10000 read, 5518 write accesses @779096
+system.cpu7: completed 20000 read, 10973 write accesses @1520367
+system.cpu4: completed 20000 read, 10979 write accesses @1526709
+system.cpu6: completed 20000 read, 11106 write accesses @1529725
+system.cpu2: completed 20000 read, 10993 write accesses @1531224
+system.cpu1: completed 20000 read, 11181 write accesses @1533339
+system.cpu5: completed 20000 read, 11353 write accesses @1534479
+system.cpu0: completed 20000 read, 11156 write accesses @1538403
+system.cpu3: completed 20000 read, 11059 write accesses @1546200
+system.cpu7: completed 30000 read, 16565 write accesses @2285511
+system.cpu5: completed 30000 read, 16777 write accesses @2288641
+system.cpu2: completed 30000 read, 16597 write accesses @2294136
+system.cpu4: completed 30000 read, 16631 write accesses @2299512
+system.cpu0: completed 30000 read, 16690 write accesses @2299577
+system.cpu1: completed 30000 read, 16784 write accesses @2300367
+system.cpu3: completed 30000 read, 16611 write accesses @2300731
+system.cpu6: completed 30000 read, 16728 write accesses @2302250
+system.cpu4: completed 40000 read, 22149 write accesses @3049466
+system.cpu6: completed 40000 read, 22257 write accesses @3061175
+system.cpu7: completed 40000 read, 22207 write accesses @3063273
+system.cpu5: completed 40000 read, 22390 write accesses @3065947
+system.cpu2: completed 40000 read, 22266 write accesses @3066692
+system.cpu3: completed 40000 read, 22073 write accesses @3067947
+system.cpu0: completed 40000 read, 22351 write accesses @3070634
+system.cpu1: completed 40000 read, 22419 write accesses @3080538
+system.cpu4: completed 50000 read, 27758 write accesses @3814226
+system.cpu5: completed 50000 read, 27788 write accesses @3821800
+system.cpu2: completed 50000 read, 27879 write accesses @3832783
+system.cpu6: completed 50000 read, 27794 write accesses @3833668
+system.cpu7: completed 50000 read, 27831 write accesses @3833943
+system.cpu3: completed 50000 read, 27630 write accesses @3836295
+system.cpu1: completed 50000 read, 28014 write accesses @3838264
+system.cpu0: completed 50000 read, 27900 write accesses @3845606
+system.cpu4: completed 60000 read, 33195 write accesses @4581871
+system.cpu6: completed 60000 read, 33436 write accesses @4591130
+system.cpu5: completed 60000 read, 33441 write accesses @4592195
+system.cpu2: completed 60000 read, 33425 write accesses @4596449
+system.cpu7: completed 60000 read, 33475 write accesses @4602310
+system.cpu1: completed 60000 read, 33528 write accesses @4604165
+system.cpu3: completed 60000 read, 33269 write accesses @4608944
+system.cpu0: completed 60000 read, 33561 write accesses @4617814
+system.cpu4: completed 70000 read, 38745 write accesses @5357021
+system.cpu1: completed 70000 read, 39092 write accesses @5358188
+system.cpu7: completed 70000 read, 39078 write accesses @5359639
+system.cpu6: completed 70000 read, 39017 write accesses @5360015
+system.cpu5: completed 70000 read, 39077 write accesses @5360709
+system.cpu2: completed 70000 read, 39142 write accesses @5362206
+system.cpu3: completed 70000 read, 38953 write accesses @5383557
+system.cpu0: completed 70000 read, 39148 write accesses @5384346
+system.cpu1: completed 80000 read, 44697 write accesses @6109229
+system.cpu4: completed 80000 read, 44391 write accesses @6113222
+system.cpu6: completed 80000 read, 44634 write accesses @6116932
+system.cpu2: completed 80000 read, 44686 write accesses @6124384
+system.cpu7: completed 80000 read, 44658 write accesses @6130030
+system.cpu5: completed 80000 read, 44817 write accesses @6133468
+system.cpu0: completed 80000 read, 44666 write accesses @6150195
+system.cpu3: completed 80000 read, 44619 write accesses @6165694
+system.cpu1: completed 90000 read, 50286 write accesses @6886139
+system.cpu5: completed 90000 read, 50291 write accesses @6887562
+system.cpu6: completed 90000 read, 50249 write accesses @6888221
+system.cpu4: completed 90000 read, 50068 write accesses @6890175
+system.cpu2: completed 90000 read, 50264 write accesses @6897909
+system.cpu7: completed 90000 read, 50336 write accesses @6907186
+system.cpu3: completed 90000 read, 50220 write accesses @6927421
+system.cpu0: completed 90000 read, 50337 write accesses @6930851
+system.cpu5: completed 100000 read, 55860 write accesses @7645897
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini

index c165a68327478bf01b9bc7855d8a18774ccec901..319711992857d5ac8bcabff735eb86bd6580d23b 100644 (file)
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000
  
  [system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr

index 78259ab685fe7be83f0dff5559bbb8fa8939e392..1e742ef57382b96bd50d7d6bc5db9d560e1fefe5 100755 (executable)
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
      0.072760 rounded to 0
  warn: rounding error > tolerance
      0.072760 rounded to 0
-system.cpu3: completed 10000 read, 5373 write accesses @610961
-system.cpu5: completed 10000 read, 5365 write accesses @611018
-system.cpu4: completed 10000 read, 5553 write accesses @613027
-system.cpu2: completed 10000 read, 5350 write accesses @617677
-system.cpu1: completed 10000 read, 5430 write accesses @618344
-system.cpu0: completed 10000 read, 5583 write accesses @619157
-system.cpu7: completed 10000 read, 5389 write accesses @620153
-system.cpu6: completed 10000 read, 5612 write accesses @620650
-system.cpu5: completed 20000 read, 10789 write accesses @1225454
-system.cpu1: completed 20000 read, 10846 write accesses @1236230
-system.cpu4: completed 20000 read, 10993 write accesses @1237289
-system.cpu0: completed 20000 read, 11135 write accesses @1237437
-system.cpu7: completed 20000 read, 10790 write accesses @1238914
-system.cpu3: completed 20000 read, 10722 write accesses @1239177
-system.cpu6: completed 20000 read, 11153 write accesses @1244507
-system.cpu2: completed 20000 read, 10728 write accesses @1245295
-system.cpu5: completed 30000 read, 16089 write accesses @1837067
-system.cpu1: completed 30000 read, 16220 write accesses @1844516
-system.cpu3: completed 30000 read, 16042 write accesses @1846213
-system.cpu6: completed 30000 read, 16442 write accesses @1852618
-system.cpu0: completed 30000 read, 16510 write accesses @1857227
-system.cpu7: completed 30000 read, 16238 write accesses @1862399
-system.cpu2: completed 30000 read, 16227 write accesses @1874504
-system.cpu4: completed 30000 read, 16481 write accesses @1879909
-system.cpu5: completed 40000 read, 21666 write accesses @2447180
-system.cpu1: completed 40000 read, 21716 write accesses @2464865
-system.cpu0: completed 40000 read, 21907 write accesses @2473366
-system.cpu7: completed 40000 read, 21535 write accesses @2473664
-system.cpu3: completed 40000 read, 21446 write accesses @2475585
-system.cpu6: completed 40000 read, 21928 write accesses @2479522
-system.cpu4: completed 40000 read, 21651 write accesses @2491724
-system.cpu2: completed 40000 read, 21571 write accesses @2492947
-system.cpu5: completed 50000 read, 27225 write accesses @3067865
-system.cpu7: completed 50000 read, 26823 write accesses @3086290
-system.cpu3: completed 50000 read, 26661 write accesses @3087077
-system.cpu1: completed 50000 read, 27045 write accesses @3088502
-system.cpu6: completed 50000 read, 27350 write accesses @3091373
-system.cpu0: completed 50000 read, 27240 write accesses @3099902
-system.cpu4: completed 50000 read, 27063 write accesses @3101501
-system.cpu2: completed 50000 read, 27064 write accesses @3114914
-system.cpu5: completed 60000 read, 32586 write accesses @3679414
-system.cpu1: completed 60000 read, 32546 write accesses @3694760
-system.cpu3: completed 60000 read, 32032 write accesses @3702088
-system.cpu7: completed 60000 read, 32061 write accesses @3707072
-system.cpu0: completed 60000 read, 32607 write accesses @3710014
-system.cpu2: completed 60000 read, 32411 write accesses @3717514
-system.cpu6: completed 60000 read, 32905 write accesses @3719411
-system.cpu4: completed 60000 read, 32455 write accesses @3724218
-system.cpu1: completed 70000 read, 37971 write accesses @4303479
-system.cpu3: completed 70000 read, 37478 write accesses @4307612
-system.cpu5: completed 70000 read, 38121 write accesses @4312096
-system.cpu0: completed 70000 read, 38044 write accesses @4316156
-system.cpu7: completed 70000 read, 37345 write accesses @4323040
-system.cpu2: completed 70000 read, 37853 write accesses @4334714
-system.cpu6: completed 70000 read, 38341 write accesses @4338265
-system.cpu4: completed 70000 read, 37883 write accesses @4348139
-system.cpu3: completed 80000 read, 42790 write accesses @4909950
-system.cpu0: completed 80000 read, 43447 write accesses @4922258
-system.cpu1: completed 80000 read, 43458 write accesses @4929896
-system.cpu5: completed 80000 read, 43556 write accesses @4929946
-system.cpu7: completed 80000 read, 42733 write accesses @4945136
-system.cpu2: completed 80000 read, 43278 write accesses @4954988
-system.cpu6: completed 80000 read, 43794 write accesses @4962728
-system.cpu4: completed 80000 read, 43313 write accesses @4970893
-system.cpu3: completed 90000 read, 48235 write accesses @5529277
-system.cpu1: completed 90000 read, 48908 write accesses @5532854
-system.cpu0: completed 90000 read, 48795 write accesses @5538200
-system.cpu5: completed 90000 read, 49134 write accesses @5544337
-system.cpu2: completed 90000 read, 48427 write accesses @5551687
-system.cpu7: completed 90000 read, 48273 write accesses @5561660
-system.cpu4: completed 90000 read, 48720 write accesses @5589754
-system.cpu6: completed 90000 read, 49134 write accesses @5592253
-system.cpu0: completed 100000 read, 54250 write accesses @6151475
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+system.cpu5: completed 10000 read, 5530 write accesses @619922
+system.cpu6: completed 10000 read, 5474 write accesses @621650
+system.cpu7: completed 10000 read, 5669 write accesses @623678
+system.cpu2: completed 10000 read, 5566 write accesses @627878
+system.cpu4: completed 10000 read, 5488 write accesses @628250
+system.cpu1: completed 10000 read, 5485 write accesses @629308
+system.cpu3: completed 10000 read, 5616 write accesses @630755
+system.cpu0: completed 10000 read, 5556 write accesses @631832
+system.cpu0: completed 20000 read, 11113 write accesses @1242739
+system.cpu2: completed 20000 read, 11184 write accesses @1249193
+system.cpu5: completed 20000 read, 11055 write accesses @1252676
+system.cpu1: completed 20000 read, 11025 write accesses @1255481
+system.cpu6: completed 20000 read, 10958 write accesses @1259795
+system.cpu3: completed 20000 read, 11192 write accesses @1262410
+system.cpu4: completed 20000 read, 11069 write accesses @1265165
+system.cpu7: completed 20000 read, 11154 write accesses @1271872
+system.cpu2: completed 30000 read, 16789 write accesses @1882328
+system.cpu5: completed 30000 read, 16628 write accesses @1882366
+system.cpu4: completed 30000 read, 16634 write accesses @1884079
+system.cpu0: completed 30000 read, 16724 write accesses @1885096
+system.cpu1: completed 30000 read, 16623 write accesses @1888139
+system.cpu3: completed 30000 read, 16738 write accesses @1892924
+system.cpu6: completed 30000 read, 16532 write accesses @1894586
+system.cpu7: completed 30000 read, 16931 write accesses @1919912
+system.cpu0: completed 40000 read, 22182 write accesses @2505116
+system.cpu4: completed 40000 read, 22117 write accesses @2510993
+system.cpu1: completed 40000 read, 22260 write accesses @2513447
+system.cpu5: completed 40000 read, 22212 write accesses @2514125
+system.cpu3: completed 40000 read, 22396 write accesses @2516765
+system.cpu2: completed 40000 read, 22468 write accesses @2519189
+system.cpu6: completed 40000 read, 22230 write accesses @2538281
+system.cpu7: completed 40000 read, 22488 write accesses @2557526
+system.cpu0: completed 50000 read, 27789 write accesses @3133555
+system.cpu2: completed 50000 read, 28077 write accesses @3139915
+system.cpu4: completed 50000 read, 27742 write accesses @3146518
+system.cpu1: completed 50000 read, 27886 write accesses @3150027
+system.cpu5: completed 50000 read, 27798 write accesses @3154334
+system.cpu3: completed 50000 read, 28034 write accesses @3161717
+system.cpu6: completed 50000 read, 27710 write accesses @3168082
+system.cpu7: completed 50000 read, 28032 write accesses @3187555
+system.cpu0: completed 60000 read, 33311 write accesses @3767660
+system.cpu4: completed 60000 read, 33304 write accesses @3772541
+system.cpu1: completed 60000 read, 33446 write accesses @3773198
+system.cpu2: completed 60000 read, 33652 write accesses @3776350
+system.cpu5: completed 60000 read, 33271 write accesses @3781457
+system.cpu6: completed 60000 read, 33278 write accesses @3794854
+system.cpu3: completed 60000 read, 33612 write accesses @3795827
+system.cpu7: completed 60000 read, 33548 write accesses @3811016
+system.cpu0: completed 70000 read, 38763 write accesses @4391942
+system.cpu5: completed 70000 read, 38783 write accesses @4406065
+system.cpu4: completed 70000 read, 38931 write accesses @4406093
+system.cpu1: completed 70000 read, 39120 write accesses @4408424
+system.cpu2: completed 70000 read, 39282 write accesses @4411507
+system.cpu6: completed 70000 read, 38935 write accesses @4431425
+system.cpu3: completed 70000 read, 39112 write accesses @4436411
+system.cpu7: completed 70000 read, 39053 write accesses @4450257
+system.cpu4: completed 80000 read, 44397 write accesses @5015840
+system.cpu0: completed 80000 read, 44355 write accesses @5031328
+system.cpu1: completed 80000 read, 44681 write accesses @5033509
+system.cpu5: completed 80000 read, 44411 write accesses @5035544
+system.cpu2: completed 80000 read, 44867 write accesses @5051495
+system.cpu6: completed 80000 read, 44501 write accesses @5065596
+system.cpu3: completed 80000 read, 44674 write accesses @5067973
+system.cpu7: completed 80000 read, 44457 write accesses @5071578
+system.cpu5: completed 90000 read, 50018 write accesses @5653124
+system.cpu4: completed 90000 read, 50091 write accesses @5657891
+system.cpu0: completed 90000 read, 50057 write accesses @5659483
+system.cpu1: completed 90000 read, 50245 write accesses @5662169
+system.cpu2: completed 90000 read, 50468 write accesses @5689246
+system.cpu7: completed 90000 read, 50055 write accesses @5700359
+system.cpu6: completed 90000 read, 50091 write accesses @5701022
+system.cpu3: completed 90000 read, 50159 write accesses @5709281
+system.cpu0: completed 100000 read, 55570 write accesses @6284915
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini

index 77392538d5ac57fe19fa7073039618f3a1d15f91..c8c135618d1903c2d2b513c3549e4500f20da288 100644 (file)
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000
  
  [system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr

index f2f8ae71ce5703ea5aa7b5259d0b85e110ae255d..80cafee6396ba09c3df3ca031b5ddc31b655a9c7 100755 (executable)
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
      0.072760 rounded to 0
  warn: rounding error > tolerance
      0.072760 rounded to 0
-system.cpu5: completed 10000 read, 5516 write accesses @570851
-system.cpu3: completed 10000 read, 5324 write accesses @572812
-system.cpu1: completed 10000 read, 5481 write accesses @576530
-system.cpu2: completed 10000 read, 5411 write accesses @581924
-system.cpu6: completed 10000 read, 5498 write accesses @589277
-system.cpu4: completed 10000 read, 5455 write accesses @592697
-system.cpu7: completed 10000 read, 5509 write accesses @593396
-system.cpu0: completed 10000 read, 5411 write accesses @595334
-system.cpu5: completed 20000 read, 10869 write accesses @1154450
-system.cpu3: completed 20000 read, 10943 write accesses @1161279
-system.cpu1: completed 20000 read, 10969 write accesses @1165235
-system.cpu2: completed 20000 read, 10883 write accesses @1170873
-system.cpu4: completed 20000 read, 10908 write accesses @1171882
-system.cpu0: completed 20000 read, 10807 write accesses @1172431
-system.cpu6: completed 20000 read, 10859 write accesses @1174037
-system.cpu7: completed 20000 read, 11017 write accesses @1183706
-system.cpu5: completed 30000 read, 16441 write accesses @1743020
-system.cpu3: completed 30000 read, 16218 write accesses @1743361
-system.cpu0: completed 30000 read, 16106 write accesses @1749355
-system.cpu6: completed 30000 read, 16285 write accesses @1751262
-system.cpu2: completed 30000 read, 16334 write accesses @1752944
-system.cpu1: completed 30000 read, 16624 write accesses @1754412
-system.cpu4: completed 30000 read, 16300 write accesses @1756493
-system.cpu7: completed 30000 read, 16545 write accesses @1761662
-system.cpu5: completed 40000 read, 21903 write accesses @2321871
-system.cpu2: completed 40000 read, 21777 write accesses @2328122
-system.cpu6: completed 40000 read, 21684 write accesses @2328788
-system.cpu0: completed 40000 read, 21584 write accesses @2333159
-system.cpu4: completed 40000 read, 21691 write accesses @2333509
-system.cpu3: completed 40000 read, 21802 write accesses @2335052
-system.cpu1: completed 40000 read, 21911 write accesses @2336699
-system.cpu7: completed 40000 read, 21984 write accesses @2354153
-system.cpu3: completed 50000 read, 27199 write accesses @2900098
-system.cpu6: completed 50000 read, 26980 write accesses @2908928
-system.cpu2: completed 50000 read, 27238 write accesses @2909195
-system.cpu5: completed 50000 read, 27250 write accesses @2913605
-system.cpu4: completed 50000 read, 26997 write accesses @2920489
-system.cpu0: completed 50000 read, 27072 write accesses @2924735
-system.cpu1: completed 50000 read, 27407 write accesses @2925503
-system.cpu7: completed 50000 read, 27387 write accesses @2927681
-system.cpu2: completed 60000 read, 32632 write accesses @3474793
-system.cpu6: completed 60000 read, 32472 write accesses @3482759
-system.cpu3: completed 60000 read, 32504 write accesses @3487367
-system.cpu0: completed 60000 read, 32401 write accesses @3493294
-system.cpu4: completed 60000 read, 32171 write accesses @3498890
-system.cpu5: completed 60000 read, 32778 write accesses @3503066
-system.cpu1: completed 60000 read, 32891 write accesses @3509381
-system.cpu7: completed 60000 read, 32765 write accesses @3516772
-system.cpu2: completed 70000 read, 38066 write accesses @4058828
-system.cpu3: completed 70000 read, 37916 write accesses @4058910
-system.cpu6: completed 70000 read, 37885 write accesses @4063852
-system.cpu4: completed 70000 read, 37622 write accesses @4080369
-system.cpu0: completed 70000 read, 37925 write accesses @4085861
-system.cpu5: completed 70000 read, 38249 write accesses @4094801
-system.cpu1: completed 70000 read, 38488 write accesses @4095495
-system.cpu7: completed 70000 read, 38117 write accesses @4097708
-system.cpu2: completed 80000 read, 43433 write accesses @4639406
-system.cpu3: completed 80000 read, 43416 write accesses @4647614
-system.cpu6: completed 80000 read, 43333 write accesses @4648301
-system.cpu5: completed 80000 read, 43562 write accesses @4662354
-system.cpu0: completed 80000 read, 43227 write accesses @4664558
-system.cpu4: completed 80000 read, 43117 write accesses @4665549
-system.cpu1: completed 80000 read, 43838 write accesses @4675271
-system.cpu7: completed 80000 read, 43557 write accesses @4676998
-system.cpu2: completed 90000 read, 48793 write accesses @5208478
-system.cpu3: completed 90000 read, 48771 write accesses @5220479
-system.cpu6: completed 90000 read, 48900 write accesses @5227295
-system.cpu5: completed 90000 read, 48930 write accesses @5242795
-system.cpu1: completed 90000 read, 49220 write accesses @5246394
-system.cpu0: completed 90000 read, 48602 write accesses @5246963
-system.cpu4: completed 90000 read, 48456 write accesses @5248509
-system.cpu7: completed 90000 read, 48936 write accesses @5260982
-system.cpu2: completed 100000 read, 54294 write accesses @5795833
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+system.cpu4: completed 10000 read, 5516 write accesses @584228
+system.cpu5: completed 10000 read, 5515 write accesses @587183
+system.cpu1: completed 10000 read, 5491 write accesses @591446
+system.cpu7: completed 10000 read, 5626 write accesses @595409
+system.cpu2: completed 10000 read, 5637 write accesses @596437
+system.cpu6: completed 10000 read, 5437 write accesses @597608
+system.cpu3: completed 10000 read, 5738 write accesses @597986
+system.cpu0: completed 10000 read, 5730 write accesses @601184
+system.cpu4: completed 20000 read, 11120 write accesses @1170250
+system.cpu6: completed 20000 read, 10900 write accesses @1171579
+system.cpu3: completed 20000 read, 11193 write accesses @1184267
+system.cpu1: completed 20000 read, 11047 write accesses @1190135
+system.cpu5: completed 20000 read, 11070 write accesses @1191953
+system.cpu7: completed 20000 read, 11317 write accesses @1192073
+system.cpu2: completed 20000 read, 11059 write accesses @1192934
+system.cpu0: completed 20000 read, 11218 write accesses @1196582
+system.cpu6: completed 30000 read, 16404 write accesses @1756097
+system.cpu4: completed 30000 read, 16698 write accesses @1768219
+system.cpu7: completed 30000 read, 16835 write accesses @1769427
+system.cpu3: completed 30000 read, 16672 write accesses @1773026
+system.cpu1: completed 30000 read, 16602 write accesses @1773962
+system.cpu0: completed 30000 read, 16781 write accesses @1777262
+system.cpu5: completed 30000 read, 16565 write accesses @1782900
+system.cpu2: completed 30000 read, 16614 write accesses @1785263
+system.cpu6: completed 40000 read, 22003 write accesses @2340507
+system.cpu1: completed 40000 read, 22145 write accesses @2358116
+system.cpu0: completed 40000 read, 22355 write accesses @2364775
+system.cpu7: completed 40000 read, 22565 write accesses @2374538
+system.cpu2: completed 40000 read, 22222 write accesses @2375711
+system.cpu4: completed 40000 read, 22294 write accesses @2376781
+system.cpu3: completed 40000 read, 22360 write accesses @2377205
+system.cpu5: completed 40000 read, 22099 write accesses @2379118
+system.cpu6: completed 50000 read, 27600 write accesses @2941333
+system.cpu1: completed 50000 read, 27821 write accesses @2946145
+system.cpu0: completed 50000 read, 27935 write accesses @2959151
+system.cpu2: completed 50000 read, 27794 write accesses @2968804
+system.cpu3: completed 50000 read, 27849 write accesses @2971166
+system.cpu5: completed 50000 read, 27657 write accesses @2977357
+system.cpu4: completed 50000 read, 27828 write accesses @2978259
+system.cpu7: completed 50000 read, 28284 write accesses @2978857
+system.cpu6: completed 60000 read, 33178 write accesses @3536924
+system.cpu1: completed 60000 read, 33394 write accesses @3543961
+system.cpu2: completed 60000 read, 33230 write accesses @3549333
+system.cpu0: completed 60000 read, 33564 write accesses @3564287
+system.cpu3: completed 60000 read, 33336 write accesses @3569137
+system.cpu4: completed 60000 read, 33587 write accesses @3570593
+system.cpu5: completed 60000 read, 33166 write accesses @3576647
+system.cpu7: completed 60000 read, 33832 write accesses @3577075
+system.cpu6: completed 70000 read, 38652 write accesses @4137461
+system.cpu2: completed 70000 read, 38824 write accesses @4141010
+system.cpu1: completed 70000 read, 39043 write accesses @4142171
+system.cpu4: completed 70000 read, 39136 write accesses @4148986
+system.cpu5: completed 70000 read, 38716 write accesses @4161730
+system.cpu0: completed 70000 read, 39119 write accesses @4165271
+system.cpu3: completed 70000 read, 38875 write accesses @4169555
+system.cpu7: completed 70000 read, 39501 write accesses @4176068
+system.cpu6: completed 80000 read, 44287 write accesses @4740297
+system.cpu2: completed 80000 read, 44433 write accesses @4742323
+system.cpu4: completed 80000 read, 44799 write accesses @4743294
+system.cpu0: completed 80000 read, 44555 write accesses @4750388
+system.cpu1: completed 80000 read, 44835 write accesses @4751884
+system.cpu5: completed 80000 read, 44235 write accesses @4755731
+system.cpu3: completed 80000 read, 44536 write accesses @4756531
+system.cpu7: completed 80000 read, 45051 write accesses @4789789
+system.cpu2: completed 90000 read, 50085 write accesses @5331779
+system.cpu1: completed 90000 read, 50520 write accesses @5335067
+system.cpu6: completed 90000 read, 50077 write accesses @5343428
+system.cpu4: completed 90000 read, 50348 write accesses @5344112
+system.cpu5: completed 90000 read, 49814 write accesses @5348125
+system.cpu3: completed 90000 read, 50170 write accesses @5349617
+system.cpu0: completed 90000 read, 50102 write accesses @5350612
+system.cpu7: completed 90000 read, 50733 write accesses @5394074
+system.cpu1: completed 100000 read, 56034 write accesses @5920895
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini

index 12c7c969e1fa4af05fd6a58effce08106077cd2c..0a7886e85eef7dfcf31bc8f7a45152cf1f1036d4 100644 (file)
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -220,7 +220,7 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000
  
  [system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr

index 5a7e36bf97611f3dd87fcf317942db0211cadb84..b3b846e79d14bc9ab74ed2a0daa2d000a2a26ab3 100755 (executable)
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
@@ -6,76 +6,80 @@ warn: rounding error > tolerance
      0.072760 rounded to 0
  warn: rounding error > tolerance
      0.072760 rounded to 0
-system.cpu4: completed 10000 read, 5267 write accesses @855219
-system.cpu7: completed 10000 read, 5381 write accesses @861031
-system.cpu1: completed 10000 read, 5262 write accesses @863126
-system.cpu2: completed 10000 read, 5381 write accesses @864460
-system.cpu0: completed 10000 read, 5401 write accesses @867419
-system.cpu3: completed 10000 read, 5382 write accesses @869141
-system.cpu5: completed 10000 read, 5455 write accesses @872828
-system.cpu6: completed 10000 read, 5482 write accesses @879392
-system.cpu7: completed 20000 read, 10628 write accesses @1724117
-system.cpu2: completed 20000 read, 10953 write accesses @1730360
-system.cpu1: completed 20000 read, 10550 write accesses @1730621
-system.cpu3: completed 20000 read, 10808 write accesses @1733195
-system.cpu4: completed 20000 read, 10816 write accesses @1737229
-system.cpu0: completed 20000 read, 10790 write accesses @1746955
-system.cpu6: completed 20000 read, 11016 write accesses @1749077
-system.cpu5: completed 20000 read, 10800 write accesses @1759742
-system.cpu3: completed 30000 read, 16255 write accesses @2586824
-system.cpu7: completed 30000 read, 15936 write accesses @2587214
-system.cpu0: completed 30000 read, 16091 write accesses @2589409
-system.cpu2: completed 30000 read, 16288 write accesses @2595682
-system.cpu4: completed 30000 read, 16193 write accesses @2610317
-system.cpu6: completed 30000 read, 16368 write accesses @2614352
-system.cpu5: completed 30000 read, 16095 write accesses @2624564
-system.cpu1: completed 30000 read, 16153 write accesses @2637701
-system.cpu7: completed 40000 read, 21310 write accesses @3438977
-system.cpu0: completed 40000 read, 21543 write accesses @3451234
-system.cpu2: completed 40000 read, 21712 write accesses @3460847
-system.cpu3: completed 40000 read, 21652 write accesses @3468818
-system.cpu6: completed 40000 read, 21709 write accesses @3479513
-system.cpu4: completed 40000 read, 21724 write accesses @3497567
-system.cpu5: completed 40000 read, 21477 write accesses @3498797
-system.cpu1: completed 40000 read, 21640 write accesses @3521390
-system.cpu7: completed 50000 read, 26683 write accesses @4309027
-system.cpu2: completed 50000 read, 27008 write accesses @4319999
-system.cpu0: completed 50000 read, 26993 write accesses @4330940
-system.cpu6: completed 50000 read, 27072 write accesses @4336165
-system.cpu3: completed 50000 read, 27085 write accesses @4352827
-system.cpu5: completed 50000 read, 26964 write accesses @4357459
-system.cpu4: completed 50000 read, 27198 write accesses @4384075
-system.cpu1: completed 50000 read, 27029 write accesses @4398757
-system.cpu7: completed 60000 read, 32063 write accesses @5160248
-system.cpu0: completed 60000 read, 32443 write accesses @5203475
-system.cpu2: completed 60000 read, 32367 write accesses @5205683
-system.cpu6: completed 60000 read, 32517 write accesses @5225171
-system.cpu3: completed 60000 read, 32534 write accesses @5227022
-system.cpu5: completed 60000 read, 32552 write accesses @5229640
-system.cpu1: completed 60000 read, 32592 write accesses @5258417
-system.cpu4: completed 60000 read, 32682 write accesses @5263781
-system.cpu7: completed 70000 read, 37467 write accesses @6033043
-system.cpu0: completed 70000 read, 37995 write accesses @6081225
-system.cpu6: completed 70000 read, 37873 write accesses @6089309
-system.cpu3: completed 70000 read, 38002 write accesses @6091981
-system.cpu2: completed 70000 read, 37862 write accesses @6093259
-system.cpu5: completed 70000 read, 38035 write accesses @6114916
-system.cpu1: completed 70000 read, 38024 write accesses @6119174
-system.cpu4: completed 70000 read, 38117 write accesses @6129370
-system.cpu7: completed 80000 read, 42779 write accesses @6903893
-system.cpu0: completed 80000 read, 43420 write accesses @6927865
-system.cpu6: completed 80000 read, 43280 write accesses @6952004
-system.cpu3: completed 80000 read, 43445 write accesses @6966407
-system.cpu5: completed 80000 read, 43493 write accesses @6966458
-system.cpu2: completed 80000 read, 43456 write accesses @6967571
-system.cpu1: completed 80000 read, 43311 write accesses @6981707
-system.cpu4: completed 80000 read, 43712 write accesses @7010960
-system.cpu7: completed 90000 read, 48212 write accesses @7781504
-system.cpu0: completed 90000 read, 49018 write accesses @7809551
-system.cpu6: completed 90000 read, 48768 write accesses @7821401
-system.cpu2: completed 90000 read, 48919 write accesses @7841558
-system.cpu1: completed 90000 read, 48631 write accesses @7843811
-system.cpu3: completed 90000 read, 49017 write accesses @7850422
-system.cpu5: completed 90000 read, 49075 write accesses @7851926
-system.cpu4: completed 90000 read, 49432 write accesses @7874435
-system.cpu7: completed 100000 read, 53796 write accesses @8664886
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+system.cpu0: completed 10000 read, 5556 write accesses @879323
+system.cpu7: completed 10000 read, 5668 write accesses @879866
+system.cpu4: completed 10000 read, 5446 write accesses @880130
+system.cpu2: completed 10000 read, 5618 write accesses @882610
+system.cpu3: completed 10000 read, 5567 write accesses @889766
+system.cpu5: completed 10000 read, 5601 write accesses @889804
+system.cpu6: completed 10000 read, 5691 write accesses @907393
+system.cpu1: completed 10000 read, 5703 write accesses @911150
+system.cpu0: completed 20000 read, 11066 write accesses @1759277
+system.cpu7: completed 20000 read, 11260 write accesses @1770595
+system.cpu4: completed 20000 read, 11011 write accesses @1777119
+system.cpu2: completed 20000 read, 11410 write accesses @1779287
+system.cpu3: completed 20000 read, 11162 write accesses @1783007
+system.cpu5: completed 20000 read, 11166 write accesses @1789252
+system.cpu6: completed 20000 read, 11205 write accesses @1795677
+system.cpu1: completed 20000 read, 11246 write accesses @1799288
+system.cpu0: completed 30000 read, 16538 write accesses @2628765
+system.cpu4: completed 30000 read, 16331 write accesses @2649038
+system.cpu3: completed 30000 read, 16729 write accesses @2656841
+system.cpu7: completed 30000 read, 16821 write accesses @2657779
+system.cpu2: completed 30000 read, 16942 write accesses @2665738
+system.cpu6: completed 30000 read, 16767 write accesses @2683028
+system.cpu5: completed 30000 read, 16740 write accesses @2683223
+system.cpu1: completed 30000 read, 16843 write accesses @2687354
+system.cpu0: completed 40000 read, 21978 write accesses @3518323
+system.cpu4: completed 40000 read, 21923 write accesses @3532643
+system.cpu2: completed 40000 read, 22312 write accesses @3539629
+system.cpu7: completed 40000 read, 22397 write accesses @3540563
+system.cpu3: completed 40000 read, 22394 write accesses @3545743
+system.cpu1: completed 40000 read, 22522 write accesses @3569491
+system.cpu6: completed 40000 read, 22217 write accesses @3571115
+system.cpu5: completed 40000 read, 22361 write accesses @3575245
+system.cpu0: completed 50000 read, 27412 write accesses @4395937
+system.cpu4: completed 50000 read, 27504 write accesses @4402816
+system.cpu2: completed 50000 read, 27861 write accesses @4421377
+system.cpu7: completed 50000 read, 28050 write accesses @4432946
+system.cpu3: completed 50000 read, 28057 write accesses @4453484
+system.cpu5: completed 50000 read, 28091 write accesses @4459262
+system.cpu6: completed 50000 read, 27767 write accesses @4466993
+system.cpu1: completed 50000 read, 28057 write accesses @4473556
+system.cpu0: completed 60000 read, 33045 write accesses @5302811
+system.cpu2: completed 60000 read, 33521 write accesses @5307713
+system.cpu4: completed 60000 read, 33106 write accesses @5309735
+system.cpu3: completed 60000 read, 33613 write accesses @5326889
+system.cpu7: completed 60000 read, 33738 write accesses @5327419
+system.cpu1: completed 60000 read, 33648 write accesses @5345018
+system.cpu6: completed 60000 read, 33262 write accesses @5350442
+system.cpu5: completed 60000 read, 33765 write accesses @5365882
+system.cpu4: completed 70000 read, 38688 write accesses @6177299
+system.cpu0: completed 70000 read, 38751 write accesses @6203477
+system.cpu2: completed 70000 read, 39098 write accesses @6206063
+system.cpu3: completed 70000 read, 39126 write accesses @6219412
+system.cpu1: completed 70000 read, 39169 write accesses @6222370
+system.cpu6: completed 70000 read, 38802 write accesses @6223076
+system.cpu7: completed 70000 read, 39595 write accesses @6226670
+system.cpu5: completed 70000 read, 39326 write accesses @6257626
+system.cpu4: completed 80000 read, 44383 write accesses @7068978
+system.cpu2: completed 80000 read, 44769 write accesses @7095466
+system.cpu3: completed 80000 read, 44569 write accesses @7095782
+system.cpu0: completed 80000 read, 44509 write accesses @7100023
+system.cpu6: completed 80000 read, 44542 write accesses @7108504
+system.cpu1: completed 80000 read, 44592 write accesses @7113439
+system.cpu7: completed 80000 read, 45281 write accesses @7113500
+system.cpu5: completed 80000 read, 44911 write accesses @7150684
+system.cpu4: completed 90000 read, 50048 write accesses @7961758
+system.cpu0: completed 90000 read, 49958 write accesses @7968130
+system.cpu2: completed 90000 read, 50371 write accesses @7973060
+system.cpu3: completed 90000 read, 50104 write accesses @7976843
+system.cpu7: completed 90000 read, 50805 write accesses @7986452
+system.cpu6: completed 90000 read, 50102 write accesses @7998542
+system.cpu1: completed 90000 read, 50241 write accesses @7999593
+system.cpu5: completed 90000 read, 50481 write accesses @8039612
+system.cpu7: completed 100000 read, 56250 write accesses @8851106
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini

index b9c14dc5fdd8b7146f47ca01c523900ed0db9b36..6605d530a5b647a53c8a7e2fdc6be7ea5bb4ae11 100644 (file)
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
@@ -10,13 +10,14 @@ time_sync_spin_threshold=100000000
  
  [system]
  type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem l2c membus physmem toL2Bus voltage_domain
  boot_osflags=a
  cache_line_size=64
  clk_domain=system.clk_domain
  eventq_index=0
  init_param=0
  kernel=
+kernel_addr_check=true
  load_addr_mask=1099511627775
  load_offset=0
  mem_mode=timing
@@ -37,7 +38,9 @@ system_port=system.membus.slave[1]
  [system.clk_domain]
  type=SrcClockDomain
  clock=1000
+domain_id=-1
  eventq_index=0
+init_perf_level=0
  voltage_domain=system.voltage_domain
  
  [system.cpu0]
@@ -491,11 +494,21 @@ size=32768
  [system.cpu_clk_domain]
  type=SrcClockDomain
  clock=500
+domain_id=-1
  eventq_index=0
+init_perf_level=0
  voltage_domain=system.voltage_domain
  
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
  [system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -553,7 +566,7 @@ sequential_access=false
  size=65536
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  children=snoop_filter
  clk_domain=system.clk_domain
  eventq_index=0
@@ -585,7 +598,7 @@ range=0:134217727
  port=system.membus.master[0]
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  children=snoop_filter
  clk_domain=system.cpu_clk_domain
  eventq_index=0
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr

index 70113e2a8c0536b44dbf04cba0bcc231d7081dfe..16ab1a5b8efa9ee9b0b6020a08312f63e74890f4 100755 (executable)
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
@@ -1,74 +1,73 @@
-warn: failed to generate dot output from build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/config.dot
-system.cpu6: completed 10000 read, 5415 write accesses @145109000
-system.cpu2: completed 10000 read, 5349 write accesses @145417500
-system.cpu1: completed 10000 read, 5329 write accesses @146140000
-system.cpu0: completed 10000 read, 5371 write accesses @146497000
-system.cpu4: completed 10000 read, 5466 write accesses @147507000
-system.cpu3: completed 10000 read, 5586 write accesses @147982000
-system.cpu5: completed 10000 read, 5427 write accesses @148047500
-system.cpu7: completed 10000 read, 5356 write accesses @148467500
-system.cpu6: completed 20000 read, 10673 write accesses @289538000
-system.cpu2: completed 20000 read, 10526 write accesses @290832000
-system.cpu1: completed 20000 read, 10766 write accesses @292890999
-system.cpu5: completed 20000 read, 10736 write accesses @293627000
-system.cpu7: completed 20000 read, 10730 write accesses @293693000
-system.cpu0: completed 20000 read, 10671 write accesses @294206500
-system.cpu4: completed 20000 read, 10944 write accesses @296769500
-system.cpu3: completed 20000 read, 10962 write accesses @297951000
-system.cpu2: completed 30000 read, 15840 write accesses @436954000
-system.cpu1: completed 30000 read, 16134 write accesses @439432500
-system.cpu6: completed 30000 read, 16128 write accesses @439710500
-system.cpu7: completed 30000 read, 16048 write accesses @440819000
-system.cpu5: completed 30000 read, 16126 write accesses @441698000
-system.cpu3: completed 30000 read, 16409 write accesses @444974000
-system.cpu4: completed 30000 read, 16439 write accesses @445869500
-system.cpu0: completed 30000 read, 16254 write accesses @446194000
-system.cpu2: completed 40000 read, 21231 write accesses @582932500
-system.cpu6: completed 40000 read, 21466 write accesses @586141500
-system.cpu1: completed 40000 read, 21414 write accesses @588066500
-system.cpu3: completed 40000 read, 21735 write accesses @588220000
-system.cpu5: completed 40000 read, 21572 write accesses @588767000
-system.cpu7: completed 40000 read, 21513 write accesses @590091000
-system.cpu0: completed 40000 read, 21682 write accesses @592843000
-system.cpu4: completed 40000 read, 21885 write accesses @593488000
-system.cpu2: completed 50000 read, 26639 write accesses @730512000
-system.cpu3: completed 50000 read, 26953 write accesses @733051500
-system.cpu6: completed 50000 read, 26889 write accesses @736295000
-system.cpu1: completed 50000 read, 26860 write accesses @736946500
-system.cpu4: completed 50000 read, 27157 write accesses @739104500
-system.cpu5: completed 50000 read, 27043 write accesses @739175000
-system.cpu7: completed 50000 read, 27030 write accesses @739274500
-system.cpu0: completed 50000 read, 27007 write accesses @740081999
-system.cpu2: completed 60000 read, 31935 write accesses @875520000
-system.cpu3: completed 60000 read, 32327 write accesses @878608000
-system.cpu1: completed 60000 read, 32037 write accesses @880758000
-system.cpu5: completed 60000 read, 32374 write accesses @883996500
-system.cpu4: completed 60000 read, 32578 write accesses @885209000
-system.cpu6: completed 60000 read, 32302 write accesses @886481999
-system.cpu0: completed 60000 read, 32356 write accesses @886645000
-system.cpu7: completed 60000 read, 32534 write accesses @888148500
-system.cpu3: completed 70000 read, 37577 write accesses @1026143000
-system.cpu2: completed 70000 read, 37542 write accesses @1027029999
-system.cpu1: completed 70000 read, 37457 write accesses @1029024000
-system.cpu5: completed 70000 read, 37722 write accesses @1029495500
-system.cpu6: completed 70000 read, 37640 write accesses @1032918500
-system.cpu0: completed 70000 read, 37692 write accesses @1034293500
-system.cpu7: completed 70000 read, 37955 write accesses @1034390500
-system.cpu4: completed 70000 read, 38136 write accesses @1036569000
-system.cpu3: completed 80000 read, 42898 write accesses @1173212500
-system.cpu2: completed 80000 read, 42932 write accesses @1173575000
-system.cpu1: completed 80000 read, 42886 write accesses @1177639500
-system.cpu5: completed 80000 read, 43232 write accesses @1178175000
-system.cpu0: completed 80000 read, 42958 write accesses @1178771500
-system.cpu6: completed 80000 read, 42919 write accesses @1180797000
-system.cpu7: completed 80000 read, 43430 write accesses @1183823000
-system.cpu4: completed 80000 read, 43550 write accesses @1185935999
-system.cpu2: completed 90000 read, 48239 write accesses @1319473000
-system.cpu3: completed 90000 read, 48329 write accesses @1322081500
-system.cpu1: completed 90000 read, 48223 write accesses @1323240500
-system.cpu5: completed 90000 read, 48632 write accesses @1326787000
-system.cpu0: completed 90000 read, 48351 write accesses @1327807500
-system.cpu6: completed 90000 read, 48287 write accesses @1329208000
-system.cpu7: completed 90000 read, 48796 write accesses @1329462500
-system.cpu4: completed 90000 read, 48969 write accesses @1334198500
-system.cpu2: completed 100000 read, 53603 write accesses @1466014000
+system.cpu4: completed 10000 read, 5317 write accesses @146612000
+system.cpu3: completed 10000 read, 5592 write accesses @148872500
+system.cpu7: completed 10000 read, 5446 write accesses @149754500
+system.cpu0: completed 10000 read, 5432 write accesses @150141500
+system.cpu1: completed 10000 read, 5693 write accesses @151929000
+system.cpu2: completed 10000 read, 5680 write accesses @152039000
+system.cpu6: completed 10000 read, 5624 write accesses @152462500
+system.cpu5: completed 10000 read, 5650 write accesses @153139000
+system.cpu4: completed 20000 read, 10841 write accesses @294897500
+system.cpu3: completed 20000 read, 11252 write accesses @295891500
+system.cpu0: completed 20000 read, 10771 write accesses @296321000
+system.cpu6: completed 20000 read, 11129 write accesses @300503000
+system.cpu1: completed 20000 read, 11154 write accesses @303003500
+system.cpu7: completed 20000 read, 11162 write accesses @303067000
+system.cpu5: completed 20000 read, 11275 write accesses @305007000
+system.cpu2: completed 20000 read, 11301 write accesses @305237000
+system.cpu4: completed 30000 read, 16293 write accesses @441647000
+system.cpu0: completed 30000 read, 16339 write accesses @446349998
+system.cpu6: completed 30000 read, 16630 write accesses @450155000
+system.cpu1: completed 30000 read, 16474 write accesses @451775000
+system.cpu3: completed 30000 read, 16954 write accesses @452288000
+system.cpu7: completed 30000 read, 16778 write accesses @453662000
+system.cpu5: completed 30000 read, 16839 write accesses @456398000
+system.cpu2: completed 30000 read, 16838 write accesses @457529500
+system.cpu4: completed 40000 read, 21515 write accesses @587133500
+system.cpu0: completed 40000 read, 21712 write accesses @594544000
+system.cpu6: completed 40000 read, 22199 write accesses @599911000
+system.cpu3: completed 40000 read, 22436 write accesses @600303500
+system.cpu1: completed 40000 read, 22001 write accesses @603916500
+system.cpu7: completed 40000 read, 22291 write accesses @604899500
+system.cpu5: completed 40000 read, 22433 write accesses @607477000
+system.cpu2: completed 40000 read, 22541 write accesses @610042000
+system.cpu4: completed 50000 read, 27094 write accesses @738435000
+system.cpu0: completed 50000 read, 27172 write accesses @744686500
+system.cpu3: completed 50000 read, 27887 write accesses @749000500
+system.cpu1: completed 50000 read, 27549 write accesses @751936500
+system.cpu6: completed 50000 read, 27775 write accesses @752183500
+system.cpu7: completed 50000 read, 27920 write accesses @756029000
+system.cpu5: completed 50000 read, 27984 write accesses @756496000
+system.cpu2: completed 50000 read, 27916 write accesses @758896000
+system.cpu4: completed 60000 read, 32601 write accesses @886900500
+system.cpu0: completed 60000 read, 32631 write accesses @892444000
+system.cpu1: completed 60000 read, 33102 write accesses @899938000
+system.cpu3: completed 60000 read, 33481 write accesses @900956500
+system.cpu6: completed 60000 read, 33392 write accesses @901773000
+system.cpu5: completed 60000 read, 33565 write accesses @904995500
+system.cpu2: completed 60000 read, 33466 write accesses @909744500
+system.cpu7: completed 60000 read, 33536 write accesses @910295999
+system.cpu4: completed 70000 read, 38175 write accesses @1036375499
+system.cpu0: completed 70000 read, 38106 write accesses @1040049000
+system.cpu6: completed 70000 read, 38841 write accesses @1048673000
+system.cpu1: completed 70000 read, 38668 write accesses @1049885000
+system.cpu3: completed 70000 read, 39114 write accesses @1053709500
+system.cpu5: completed 70000 read, 39200 write accesses @1055942500
+system.cpu2: completed 70000 read, 38856 write accesses @1057747499
+system.cpu7: completed 70000 read, 39064 write accesses @1059368500
+system.cpu4: completed 80000 read, 43619 write accesses @1185369000
+system.cpu0: completed 80000 read, 43549 write accesses @1189974500
+system.cpu6: completed 80000 read, 44374 write accesses @1198657499
+system.cpu1: completed 80000 read, 43973 write accesses @1199665500
+system.cpu3: completed 80000 read, 44602 write accesses @1199968000
+system.cpu5: completed 80000 read, 44843 write accesses @1207585500
+system.cpu2: completed 80000 read, 44389 write accesses @1209591000
+system.cpu7: completed 80000 read, 44629 write accesses @1211090500
+system.cpu4: completed 90000 read, 49142 write accesses @1333753500
+system.cpu0: completed 90000 read, 49249 write accesses @1339029000
+system.cpu1: completed 90000 read, 49469 write accesses @1348019000
+system.cpu6: completed 90000 read, 50013 write accesses @1351048500
+system.cpu3: completed 90000 read, 50231 write accesses @1351323000
+system.cpu5: completed 90000 read, 50311 write accesses @1355589000
+system.cpu7: completed 90000 read, 50146 write accesses @1357457500
+system.cpu2: completed 90000 read, 49997 write accesses @1360771999
+system.cpu4: completed 100000 read, 54692 write accesses @1486654500
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini

index 62f705803d77bfcd29d6a792ffc5049f8e1016d5..06da0f372ea26ecb151afe5398150a48a8536b93 100644 (file)
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
@@ -22,7 +22,7 @@ load_addr_mask=1099511627775
  load_offset=0
  mem_mode=timing
  mem_ranges=
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
  num_work_ids=16
  readfile=
  symbolfile=
@@ -508,7 +508,7 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.funcbus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -566,10 +566,11 @@ sequential_access=false
  size=65536
  
  [system.membus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=16
@@ -590,10 +591,11 @@ range=0:134217727
  port=system.membus.master[0]
  
  [system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
  clk_domain=system.cpu_clk_domain
  eventq_index=0
  header_cycles=1
+snoop_filter=Null
  system=system
  use_default_range=false
  width=16
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr

index 084f6f6abc88c7779fcf1043ef8f157230508475..b2fb4093d8289ff6eb7d51f193ee64a9479194e8 100755 (executable)
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
@@ -1,73 +1,73 @@
-system.cpu6: completed 10000 read, 5217 write accesses @68085999
-system.cpu4: completed 10000 read, 5435 write accesses @69661000
-system.cpu2: completed 10000 read, 5368 write accesses @70121500
-system.cpu3: completed 10000 read, 5457 write accesses @70317500
-system.cpu1: completed 10000 read, 5387 write accesses @70875500
-system.cpu7: completed 10000 read, 5470 write accesses @70949000
-system.cpu0: completed 10000 read, 5435 write accesses @71227500
-system.cpu5: completed 10000 read, 5514 write accesses @71894000
-system.cpu6: completed 20000 read, 10518 write accesses @132327500
-system.cpu4: completed 20000 read, 10839 write accesses @133525000
-system.cpu1: completed 20000 read, 10784 write accesses @134714500
-system.cpu7: completed 20000 read, 10701 write accesses @135318500
-system.cpu0: completed 20000 read, 10821 write accesses @135563500
-system.cpu2: completed 20000 read, 10843 write accesses @135684500
-system.cpu3: completed 20000 read, 10685 write accesses @135938500
-system.cpu5: completed 20000 read, 11031 write accesses @136425000
-system.cpu6: completed 30000 read, 16001 write accesses @197849500
-system.cpu4: completed 30000 read, 16254 write accesses @198725500
-system.cpu0: completed 30000 read, 16109 write accesses @199579499
-system.cpu1: completed 30000 read, 16209 write accesses @200016500
-system.cpu5: completed 30000 read, 16414 write accesses @200525000
-system.cpu3: completed 30000 read, 15978 write accesses @200724000
-system.cpu7: completed 30000 read, 16153 write accesses @201563500
-system.cpu2: completed 30000 read, 16316 write accesses @202401999
-system.cpu4: completed 40000 read, 21506 write accesses @263053500
-system.cpu6: completed 40000 read, 21338 write accesses @263431500
-system.cpu5: completed 40000 read, 21670 write accesses @263987000
-system.cpu3: completed 40000 read, 21219 write accesses @264608000
-system.cpu1: completed 40000 read, 21536 write accesses @265348500
-system.cpu0: completed 40000 read, 21604 write accesses @265426500
-system.cpu7: completed 40000 read, 21465 write accesses @265674000
-system.cpu2: completed 40000 read, 21690 write accesses @268754000
-system.cpu6: completed 50000 read, 26563 write accesses @327819000
-system.cpu4: completed 50000 read, 27066 write accesses @328101000
-system.cpu5: completed 50000 read, 26900 write accesses @328372000
-system.cpu3: completed 50000 read, 26596 write accesses @328811500
-system.cpu1: completed 50000 read, 26845 write accesses @328908500
-system.cpu7: completed 50000 read, 26873 write accesses @331316999
-system.cpu0: completed 50000 read, 26988 write accesses @331358000
-system.cpu2: completed 50000 read, 27102 write accesses @333876000
-system.cpu1: completed 60000 read, 32156 write accesses @392077000
-system.cpu6: completed 60000 read, 31998 write accesses @392784000
-system.cpu5: completed 60000 read, 32223 write accesses @393227500
-system.cpu4: completed 60000 read, 32446 write accesses @394175000
-system.cpu3: completed 60000 read, 32090 write accesses @394842000
-system.cpu0: completed 60000 read, 32282 write accesses @395716500
-system.cpu7: completed 60000 read, 32292 write accesses @397180000
-system.cpu2: completed 60000 read, 32266 write accesses @397288500
-system.cpu6: completed 70000 read, 37440 write accesses @457780500
-system.cpu1: completed 70000 read, 37577 write accesses @458242500
-system.cpu5: completed 70000 read, 37616 write accesses @458643500
-system.cpu4: completed 70000 read, 37952 write accesses @459569500
-system.cpu3: completed 70000 read, 37486 write accesses @460007500
-system.cpu0: completed 70000 read, 37804 write accesses @461418499
-system.cpu2: completed 70000 read, 37588 write accesses @461790000
-system.cpu7: completed 70000 read, 37743 write accesses @462130500
-system.cpu1: completed 80000 read, 42976 write accesses @523192500
-system.cpu5: completed 80000 read, 43028 write accesses @523895500
-system.cpu6: completed 80000 read, 42870 write accesses @524155000
-system.cpu4: completed 80000 read, 43341 write accesses @524226000
-system.cpu3: completed 80000 read, 42885 write accesses @524383000
-system.cpu2: completed 80000 read, 43005 write accesses @527239000
-system.cpu7: completed 80000 read, 43156 write accesses @528371000
-system.cpu0: completed 80000 read, 43239 write accesses @528519000
-system.cpu3: completed 90000 read, 48037 write accesses @586595000
-system.cpu1: completed 90000 read, 48299 write accesses @588010000
-system.cpu4: completed 90000 read, 48806 write accesses @589147500
-system.cpu6: completed 90000 read, 48454 write accesses @589844000
-system.cpu5: completed 90000 read, 48341 write accesses @590185000
-system.cpu2: completed 90000 read, 48395 write accesses @591584000
-system.cpu7: completed 90000 read, 48496 write accesses @592485000
-system.cpu0: completed 90000 read, 48680 write accesses @594831500
-system.cpu3: completed 100000 read, 53536 write accesses @652606500
+system.cpu1: completed 10000 read, 5362 write accesses @70749500
+system.cpu6: completed 10000 read, 5537 write accesses @71195000
+system.cpu7: completed 10000 read, 5519 write accesses @71360000
+system.cpu4: completed 10000 read, 5569 write accesses @71442000
+system.cpu3: completed 10000 read, 5551 write accesses @71947000
+system.cpu5: completed 10000 read, 5610 write accesses @72351000
+system.cpu2: completed 10000 read, 5548 write accesses @72366000
+system.cpu0: completed 10000 read, 5597 write accesses @72604000
+system.cpu1: completed 20000 read, 10810 write accesses @136799000
+system.cpu6: completed 20000 read, 11150 write accesses @137085000
+system.cpu4: completed 20000 read, 11041 write accesses @137243000
+system.cpu5: completed 20000 read, 11255 write accesses @138165500
+system.cpu7: completed 20000 read, 11207 write accesses @138180500
+system.cpu3: completed 20000 read, 11018 write accesses @138711500
+system.cpu2: completed 20000 read, 11094 write accesses @139138500
+system.cpu0: completed 20000 read, 11219 write accesses @140219500
+system.cpu5: completed 30000 read, 16778 write accesses @203366500
+system.cpu6: completed 30000 read, 16566 write accesses @203972500
+system.cpu4: completed 30000 read, 16724 write accesses @204003000
+system.cpu1: completed 30000 read, 16364 write accesses @204656500
+system.cpu2: completed 30000 read, 16663 write accesses @204765000
+system.cpu7: completed 30000 read, 16867 write accesses @205681500
+system.cpu3: completed 30000 read, 16606 write accesses @205970500
+system.cpu0: completed 30000 read, 16763 write accesses @207333500
+system.cpu5: completed 40000 read, 22274 write accesses @268156500
+system.cpu6: completed 40000 read, 22009 write accesses @269534000
+system.cpu2: completed 40000 read, 22255 write accesses @271458500
+system.cpu4: completed 40000 read, 22360 write accesses @272143500
+system.cpu0: completed 40000 read, 22178 write accesses @272544500
+system.cpu1: completed 40000 read, 22131 write accesses @272652000
+system.cpu3: completed 40000 read, 22246 write accesses @273210500
+system.cpu7: completed 40000 read, 22431 write accesses @273722500
+system.cpu5: completed 50000 read, 27739 write accesses @335077500
+system.cpu6: completed 50000 read, 27540 write accesses @335500500
+system.cpu4: completed 50000 read, 27805 write accesses @337842000
+system.cpu7: completed 50000 read, 27755 write accesses @337879500
+system.cpu2: completed 50000 read, 27750 write accesses @338436000
+system.cpu0: completed 50000 read, 27692 write accesses @339374000
+system.cpu1: completed 50000 read, 27828 write accesses @340225500
+system.cpu3: completed 50000 read, 27884 write accesses @341199000
+system.cpu5: completed 60000 read, 33220 write accesses @401069000
+system.cpu6: completed 60000 read, 33064 write accesses @401171000
+system.cpu7: completed 60000 read, 33318 write accesses @402700500
+system.cpu4: completed 60000 read, 33407 write accesses @404241000
+system.cpu2: completed 60000 read, 33248 write accesses @404642000
+system.cpu0: completed 60000 read, 33222 write accesses @405992500
+system.cpu1: completed 60000 read, 33452 write accesses @407711000
+system.cpu3: completed 60000 read, 33293 write accesses @408190000
+system.cpu6: completed 70000 read, 38545 write accesses @467631000
+system.cpu5: completed 70000 read, 38773 write accesses @467786500
+system.cpu7: completed 70000 read, 38817 write accesses @468768499
+system.cpu2: completed 70000 read, 38804 write accesses @470615500
+system.cpu4: completed 70000 read, 38942 write accesses @471024500
+system.cpu1: completed 70000 read, 38924 write accesses @472741500
+system.cpu0: completed 70000 read, 38792 write accesses @473888500
+system.cpu3: completed 70000 read, 38873 write accesses @474437500
+system.cpu5: completed 80000 read, 44156 write accesses @533178500
+system.cpu6: completed 80000 read, 44068 write accesses @534028500
+system.cpu7: completed 80000 read, 44398 write accesses @535850500
+system.cpu2: completed 80000 read, 44302 write accesses @537573000
+system.cpu4: completed 80000 read, 44462 write accesses @538315000
+system.cpu0: completed 80000 read, 44312 write accesses @540158500
+system.cpu1: completed 80000 read, 44676 write accesses @540667000
+system.cpu3: completed 80000 read, 44446 write accesses @541285000
+system.cpu5: completed 90000 read, 49777 write accesses @600496000
+system.cpu6: completed 90000 read, 49628 write accesses @600631500
+system.cpu7: completed 90000 read, 49999 write accesses @603063500
+system.cpu4: completed 90000 read, 49890 write accesses @603847000
+system.cpu2: completed 90000 read, 50013 write accesses @605897999
+system.cpu1: completed 90000 read, 50188 write accesses @606811500
+system.cpu3: completed 90000 read, 49928 write accesses @606922500
+system.cpu0: completed 90000 read, 49837 write accesses @607047500
+system.cpu6: completed 100000 read, 55113 write accesses @666669000
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini

index a7dfb0cb506ccb184c571a58447cb8fb9ebb5686..b1d661d27b0e79c8dd3384421bb8f65972c99e34 100644 (file)
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
@@ -67,7 +67,7 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
@@ -106,8 +106,33 @@ slave=system.cpu.port
  
  [system.physmem]
  type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
  activation_limit=4
  addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
  banks_per_rank=8
  burst_length=8
  channels=1
@@ -116,6 +141,7 @@ conf_table_reported=true
  device_bus_width=8
  device_rowbuffer_size=1024
  devices_per_rank=8
+dll=true
  eventq_index=0
  in_addr_map=true
  max_accesses_per_row=16
@@ -129,19 +155,26 @@ read_buffer_size=32
  static_backend_latency=10000
  static_frontend_latency=10000
  tBURST=5000
+tCCD_L=0
  tCK=1250
  tCL=13750
+tCS=2500
  tRAS=35000
  tRCD=13750
  tREFI=7800000
  tRFC=260000
  tRP=13750
  tRRD=6000
+tRRD_L=0
  tRTP=7500
  tRTW=2500
  tWR=15000
  tWTR=7500
  tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
  write_buffer_size=64
  write_high_thresh_perc=85
  write_low_thresh_perc=50
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini

index bda575e80ad3de858bfa2b44cf936cec517d2b38..c210da50343347dacc8755961d02b04bd576e53e 100644 (file)
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
@@ -67,7 +67,7 @@ sys_clk_domain=system.clk_domain
  transition_latency=100000000
  
  [system.membus]
-type=NoncoherentBus
+type=NoncoherentXBar
  clk_domain=system.clk_domain
  eventq_index=0
  header_cycles=1
author	Nilay Vaish <nilay@cs.wisc.edu>
	Sat, 11 Oct 2014 21:18:51 +0000 (16:18 -0500)
committer	Nilay Vaish <nilay@cs.wisc.edu>
	Sat, 11 Oct 2014 21:18:51 +0000 (16:18 -0500)
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt		patch \| blob \| history
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal		patch \| blob \| history
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini		patch \| blob \| history
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json		patch \| blob \| history
tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini		patch \| blob \| history
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini		patch \| blob \| history
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini		patch \| blob \| history
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini		patch \| blob \| history
tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini		patch \| blob \| history
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini		patch \| blob \| history
tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini		patch \| blob \| history
tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini		patch \| blob \| history
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini		patch \| blob \| history
tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini		patch \| blob \| history
tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini		patch \| blob \| history
tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini		patch \| blob \| history
tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini		patch \| blob \| history
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini		patch \| blob \| history
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini		patch \| blob \| history
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini		patch \| blob \| history
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini		patch \| blob \| history
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt		patch \| blob \| history
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini		patch \| blob \| history
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini		patch \| blob \| history
tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini		patch \| blob \| history
tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini		patch \| blob \| history
tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini		patch \| blob \| history
tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini		patch \| blob \| history
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini		patch \| blob \| history
tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini		patch \| blob \| history
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini		patch \| blob \| history
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini		patch \| blob \| history
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr	[changed mode: 0644->0755]	patch \| blob \| history
tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout	[changed mode: 0644->0755]	patch \| blob \| history
tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini		patch \| blob \| history
tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini		patch \| blob \| history
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt		patch \| blob \| history
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini		patch \| blob \| history
tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini		patch \| blob \| history
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini		patch \| blob \| history
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini		patch \| blob \| history
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini		patch \| blob \| history
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini		patch \| blob \| history
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini		patch \| blob \| history
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini		patch \| blob \| history
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout		patch \| blob \| history
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini		patch \| blob \| history
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout		patch \| blob \| history
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini		patch \| blob \| history
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini		patch \| blob \| history
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr		patch \| blob \| history
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini		patch \| blob \| history
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr		patch \| blob \| history
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini		patch \| blob \| history
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr		patch \| blob \| history
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini		patch \| blob \| history
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr		patch \| blob \| history
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini		patch \| blob \| history
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr		patch \| blob \| history
tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini		patch \| blob \| history
tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr		patch \| blob \| history
tests/quick/se/50.memtest/ref/null/none/memtest/config.ini		patch \| blob \| history
tests/quick/se/50.memtest/ref/null/none/memtest/simerr		patch \| blob \| history
tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini		patch \| blob \| history
tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini		patch \| blob \| history