soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 3847504e8a1632eb6ba9175b40bd40a61a20509c..3d466544a689e642a836447b6a9de6f920296e1f 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -323,30 +323,33 @@ class SoCCSR:
         self.logger.info(colorer("CSR Bus Handler created.", color="cyan"))
 
     # Add ------------------------------------------------------------------------------------------
-    def add(self, name, n=None):
+    def add(self, name, n=None, use_loc_if_exists=False):
         allocated = False
-        if name in self.csrs.keys():
-            self.logger.error("{} CSR name already used.".format(colorer(name, "red")))
-            self.logger.error(self)
-            raise
-        if n in self.csrs.values():
-            self.logger.error("{} CSR Location already used.".format(colorer(n, "red")))
-            self.logger.error(self)
-            raise
-        if n is None:
-            allocated = True
-            n = self.alloc(name)
-        else:
-            if n < 0:
-                self.logger.error("{} CSR Location should be positive.".format(
-                    colorer(n, color="red")))
+        if not (use_loc_if_exists and name in self.csrs.keys()):
+            if name in self.csrs.keys():
+                self.logger.error("{} CSR name already used.".format(colorer(name, "red")))
+                self.logger.error(self)
                 raise
-            if n > self.n_csrs:
-                self.logger.error("{} CSR Location too high (Up to {}).".format(
-                    colorer(n, color="red"),
-                    colorer(self.n_csrs, color="green")))
+            if n in self.csrs.values():
+                self.logger.error("{} CSR Location already used.".format(colorer(n, "red")))
+                self.logger.error(self)
                 raise
-        self.csrs[name] = n
+            if n is None:
+                allocated = True
+                n = self.alloc(name)
+            else:
+                if n < 0:
+                    self.logger.error("{} CSR Location should be positive.".format(
+                        colorer(n, color="red")))
+                    raise
+                if n > self.n_csrs:
+                    self.logger.error("{} CSR Location too high (Up to {}).".format(
+                        colorer(n, color="red"),
+                        colorer(self.n_csrs, color="green")))
+                    raise
+            self.csrs[name] = n
+        else:
+            n = self.csrs[name]
         self.logger.info("{} CSR {} at Location {}.".format(
             colorer(name, color="underline"),
             colorer("allocated" if allocated else "added", color="yellow" if allocated else "green"),

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 943c5c46d6334c728570cd5ac0ab18c008132d12..fd28b2f4067a0b40d20783ee947d4845219ffdc1 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -170,7 +170,7 @@ class SoCCore(SoC):
         # Add SoCController
         if with_ctrl:
             self.submodules.ctrl = SoCController()
-            self.add_csr("ctrl")
+            self.add_csr("ctrl", allow_user_defined=True)
 
         # Add CPU
         self.config["CPU_TYPE"] = str(cpu_type).upper()
@@ -207,7 +207,7 @@ class SoCCore(SoC):
                 self.add_wb_master(soc_bus)
 
             # Add CPU CSR (dynamic)
-            self.add_csr("cpu")
+            self.add_csr("cpu", allow_user_defined=True)
 
             # Add CPU interrupts
             for _name, _id in self.cpu.interrupts.items():
@@ -263,8 +263,8 @@ class SoCCore(SoC):
                 else:
                     self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
                 self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
-            self.add_csr("uart_phy")
-            self.add_csr("uart")
+            self.add_csr("uart_phy", allow_user_defined=True)
+            self.add_csr("uart", allow_user_defined=True)
             self.add_interrupt("uart")
 
         # Add Identifier
@@ -272,13 +272,13 @@ class SoCCore(SoC):
             if ident_version:
                 ident = ident + " " + get_version()
             self.submodules.identifier = identifier.Identifier(ident)
-            self.add_csr("identifier_mem")
+            self.add_csr("identifier_mem", allow_user_defined=True)
         self.config["CLOCK_FREQUENCY"] = int(clk_freq)
 
         # Add Timer
         if with_timer:
             self.submodules.timer0 = timer.Timer()
-            self.add_csr("timer0")
+            self.add_csr("timer0", allow_user_defined=True)
             self.add_interrupt("timer0")
 
         # Add Wishbone to CSR bridge
@@ -301,7 +301,7 @@ class SoCCore(SoC):
         self.irq.add(interrupt_name, interrupt_id)
 
     def add_csr(self, csr_name, csr_id=None, allow_user_defined=False):
-        self.csr.add(csr_name, csr_id)
+        self.csr.add(csr_name, csr_id, use_loc_if_exists=allow_user_defined)
 
     def initialize_rom(self, data):
         self.rom.mem.init = data