Fix tests/various/specify.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/tests/various/specify.v b/tests/various/specify.v
index 73a59eb7abc1457e73ddcfed7404104d9e76601b..5d44d78f76b4f51e2fbe6a55f3ef82b947eeea57 100644 (file)
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -7,9 +7,11 @@ module test (
                if (EN) Q <= D;
 
        specify
+`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
                if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
                $setup(D, posedge CLK &&& EN, 5);
                $hold(posedge CLK, D &&& EN, 6);
+`endif
        endspecify
 endmodule
 
@@ -31,14 +33,7 @@ endmodule
 
 module issue01144(input clk, d, output q);
 specify
-  // Fails:
   (posedge clk => (q +: d)) = (3,1);
-  //(/*posedge*/ clk => (q +: d)) = (3,1); // Invalid syntax
   (posedge clk *> (q +: d)) = (3,1);
-  //(/*posedge*/ clk *> (q +: d)) = (3,1); // Invalid syntax
-
-  // Works:
-  (/*posedge*/ clk => q) = (3,1);
-  (/*posedge*/ clk *> q) = (3,1);
 endspecify
 endmodule

diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index a2b6038e47e81f95701e4a55c4aaa3ffb600acda..00597e1e282c9d0ae7367b235d7cc606faec0934 100644 (file)
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -55,4 +55,4 @@ equiv_induct -seq 5
 equiv_status -assert
 design -reset
 
-read_verilog specify.v
+read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v