self.sink = sink = Sink(description)
self.source = source = Source(description)
- ###
+ # # #
+
sink_status = EndpointPacketStatus(self.sink)
source_status = EndpointPacketStatus(self.source)
self.submodules += sink_status, source_status
self.to_rx = to_rx = Source(tx_to_rx)
self.from_rx = from_rx = Sink(rx_to_tx)
- ###
+ # # #
self.comb += [
transport.sink.pm_port.eq(0),
self.to_tx = to_tx = Source(rx_to_tx)
self.from_tx = from_tx = Sink(tx_to_rx)
- ###
+ # # #
def test_type(name):
return transport.source.type == fis_types[name]
self.sink = Sink(link_description(32))
self.from_rx = Sink(from_rx)
- ###
+ # # #
self.fsm = fsm = FSM(reset_state="IDLE")
self.submodules += fsm
self.hold = Signal()
self.to_tx = Source(from_rx)
- ###
+ # # #
self.fsm = fsm = FSM(reset_state="IDLE")
self.submodules += fsm
self.sink = sink = Sink(description)
self.source = source = Source(description)
- ###
+ # # #
counter = Counter(max=4)
self.submodules += counter
self.sink = sink = Sink(description)
self.source = source = Source(description)
- ###
+ # # #
is_data = Signal()
is_cont = Signal()
self.last = Signal(width)
self.next = Signal(width)
- ###
+ # # #
def _optimize_eq(l):
"""
self.value = Signal(self.width)
self.error = Signal()
- ###
+ # # #
engine = CRCEngine(self.width, self.polynom)
self.submodules += engine
self.source = source = Source(layout)
self.busy = Signal()
- ###
+ # # #
dw = flen(sink.d)
crc = crc_class(dw)
self.source = source = Source(layout)
self.busy = Signal()
- ###
+ # # #
dw = flen(sink.d)
crc = crc_class(dw)
def __init__(self):
self.value = Signal(32)
- ###
+ # # #
context = Signal(16, reset=0xf0f6)
next_value = Signal(32)
self.sink = sink = Sink(description)
self.source = source = Source(description)
- ###
+ # # #
scrambler = Scrambler()
self.submodules += scrambler
def __init__(self, link):
self.sink = sink = Sink(transport_tx_description(32))
- ###
+ # # #
cmd_ndwords = max(fis_reg_h2d_cmd_len, fis_data_cmd_len)
encoded_cmd = Signal(cmd_ndwords*32)
def __init__(self, link):
self.source = source = Source(transport_rx_description(32))
- ###
+ # # #
cmd_ndwords = max(fis_reg_d2h_cmd_len, fis_dma_activate_d2h_cmd_len,
fis_pio_setup_d2h_cmd_len, fis_data_cmd_len)
args = _get_args()
wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
wb.open()
- ###
+ # # #
identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
except KeyboardInterrupt:
pass
- ###
+ # # #
wb.close()
checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
wb.open()
regs = wb.regs
- ###
-
+ # # #
trig = "now"
if len(sys.argv) < 2:
print("No trigger condition, triggering immediately!")
la.upload()
la.save("dump.vcd")
- ###
+ # # #
wb.close()
f = open("dump_link.txt", "w")
def main(wb):
wb.open()
regs = wb.regs
- ###
+ # # #
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
- ###
+ # # #
wb.close()
self.aborted = Signal()
self.errors = Signal(32) # Note: Not used for writes
- ###
+ # # #
source, sink = user_port.sink, user_port.source
self.aborted = Signal()
self.errors = Signal(32)
- ###
+ # # #
source, sink = user_port.sink, user_port.source
self._errors = CSRStatus(32)
self._cycles = CSRStatus(32)
- ###
+ # # #
self.submodules += bist_unit
self.submodules += fifo
self.source = fifo.source
- ###
+ # # #
source, sink = user_port.sink, user_port.source
self._source_ack = CSR()
self._source_data = CSRStatus(32)
- ###
+ # # #
self.submodules += bist_identify
self.comb += [
self.sink = sink = Sink(phy_description(32))
self.source = source = Source(phy_description(32))
- ###
+ # # #
+
self.comb += [
source.stb.eq(1),
sink.ack.eq(1)
self.sink = sink = Sink(phy_description(16))
self.source = source = Source(phy_description(32))
- ###
+ # # #
# width convertion (16 to 32) and byte alignment
byte_alignment = Signal()
self.sink = sink = Sink(phy_description(32))
self.source = source = Source(phy_description(16))
- ###
+ # # #
# clock domain crossing
# (sata_gen3) sys_clk to 300MHz sata_tx clk
self.sink = sink = Sink(phy_description(32))
self.source = source = Source(phy_description(32))
- ###
+ # # #
# send 2 ALIGN every 256 DWORDs
# used for clock compensation between
self.sink = sink = Sink(phy_description(32))
self.source = source = Source(phy_description(32))
- ###
+ # # #
charisk_match = sink.charisk == 0b0001
data_match = sink.data == primitives["ALIGN"]
self.sink = sink = Sink(phy_description(32))
self.source = source = Source(phy_description(32))
- ###
+ # # #
# TX path
align_inserter = LiteSATAPHYAlignInserter(ctrl)
"p_RX_DDI_SEL": 0,
"p_RX_DEFER_RESET_BUF_EN": "TRUE",
- #CDR Attributes
+ # CDR Attributes
"p_RXCDR_CFG": rxcdr_cfg,
"p_RXCDR_FR_RESET_ON_EIDLE": 0,
"p_RXCDR_HOLD_DURING_EIDLE": 0,
class PacketStreamer(Module):
def __init__(self, description, packet_class):
self.source = Source(description)
- ###
+
+ # # #
+
self.packets = []
self.packet = packet_class()
self.packet.done = 1
class PacketLogger(Module):
def __init__(self, description, packet_class):
self.sink = Sink(description)
- ###
+
+ # # #
+
self.packet_class = packet_class
self.packet = packet_class()
yield from self.streamer.send(streamer_packet)
yield from self.logger.receive(len(test_packet))
#for d in self.logger.packet:
- # print("%08x" %d)
+ # print("{:08}".format(d))
# check results
s, l, e = check(streamer_packet, self.logger.packet)
class PHYSource(Module):
def __init__(self):
self.source = Source(phy_description(32))
- ###
+
+ # # #
+
self.dword = PHYDword()
def send(self, dword):
class PHYSink(Module):
def __init__(self):
self.sink = Sink(phy_description(32))
- ###
+
+ # # #
+
self.dword = PHYDword()
def receive(self):
transport_debug=False, transport_loopback=False,
hdd_debug=False,
):
- ###
self.submodules.phy = PHYLayer()
self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level)
self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback)
projects / litex.git / commitdiff