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Merge pull request #802 from whitequark/write_verilog_async_mem_ports
authorClifford Wolf <clifford@clifford.at>
Tue, 12 Feb 2019 13:41:34 +0000 (14:41 +0100)
committerGitHub <noreply@github.com>
Tue, 12 Feb 2019 13:41:34 +0000 (14:41 +0100)
write_verilog: correctly emit asynchronous transparent ports


Trivial merge