dedent code section we're keeping in fcvtfgs[.] -- nothing but dedenting

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 7d61e16bb81876b3e20923a75b031784a56aee5f..713643a5fb66f51dd73242bfc52551c74f612e3a 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -488,33 +488,33 @@ Special Registers altered:
             src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
         FRT <- bfp64_CONVERT_FROM_BFP(src)
     else
-        # rounding may be necessary. based off xscvuxdsp
-        reset_xflags()
-        switch(IT)
-            case(0):  # Signed 32-bit
-                src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
-            case(1):  # Unsigned 32-bit
-                src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
-            case(2):  # Signed 64-bit
-                src <- bfp_CONVERT_FROM_SI64((RB))
-            default:  # Unsigned 64-bit
-                src <- bfp_CONVERT_FROM_UI64((RB))
-        if RCS[0] = 1 then  # Single
-            rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
-            result32 <- bfp32_CONVERT_FROM_BFP(rnd)
-            cls <- fprf_CLASS_BFP32(result32)
-            result <- DOUBLE(result32)
-        else
-            rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
-            result <- bfp64_CONVERT_FROM_BFP(rnd)
-            cls <- fprf_CLASS_BFP64(result)
+    # rounding may be necessary. based off xscvuxdsp
+    reset_xflags()
+    switch(IT)
+        case(0):  # Signed 32-bit
+            src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
+        case(1):  # Unsigned 32-bit
+            src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
+        case(2):  # Signed 64-bit
+            src <- bfp_CONVERT_FROM_SI64((RB))
+        default:  # Unsigned 64-bit
+            src <- bfp_CONVERT_FROM_UI64((RB))
+    if RCS[0] = 1 then  # Single
+        rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
+        result32 <- bfp32_CONVERT_FROM_BFP(rnd)
+        cls <- fprf_CLASS_BFP32(result32)
+        result <- DOUBLE(result32)
+    else
+        rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
+        result <- bfp64_CONVERT_FROM_BFP(rnd)
+        cls <- fprf_CLASS_BFP64(result)
 
-        if xx_flag = 1 then SetFX(FPSCR.XX)
+    if xx_flag = 1 then SetFX(FPSCR.XX)
 
-        FRT <- result
-        FPSCR.FPRF <- cls
-        FPSCR.FR <- inc_flag
-        FPSCR.FI <- xx_flag
+    FRT <- result
+    FPSCR.FPRF <- cls
+    FPSCR.FR <- inc_flag
+    FPSCR.FI <- xx_flag
 ```
 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX,
 don't remove them -->

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index c82e991a7d3d3f08f6377a067c2d8084e1e5dda9..adeac3d4fc14b1fdde596c158accd99087ac4089 100644 (file)
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -340,33 +340,33 @@ Special Registers altered:
             src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
         FRT <- bfp64_CONVERT_FROM_BFP(src)
     else
-        # rounding may be necessary. based off xscvuxdsp
-        reset_xflags()
-        switch(IT)
-            case(0):  # Signed 32-bit
-                src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
-            case(1):  # Unsigned 32-bit
-                src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
-            case(2):  # Signed 64-bit
-                src <- bfp_CONVERT_FROM_SI64((RB))
-            default:  # Unsigned 64-bit
-                src <- bfp_CONVERT_FROM_UI64((RB))
-        if RCS[0] = 1 then  # Single
-            rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
-            result32 <- bfp32_CONVERT_FROM_BFP(rnd)
-            cls <- fprf_CLASS_BFP32(result32)
-            result <- DOUBLE(result32)
-        else
-            rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
-            result <- bfp64_CONVERT_FROM_BFP(rnd)
-            cls <- fprf_CLASS_BFP64(result)
+    # rounding may be necessary. based off xscvuxdsp
+    reset_xflags()
+    switch(IT)
+        case(0):  # Signed 32-bit
+            src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
+        case(1):  # Unsigned 32-bit
+            src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
+        case(2):  # Signed 64-bit
+            src <- bfp_CONVERT_FROM_SI64((RB))
+        default:  # Unsigned 64-bit
+            src <- bfp_CONVERT_FROM_UI64((RB))
+    if RCS[0] = 1 then  # Single
+        rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
+        result32 <- bfp32_CONVERT_FROM_BFP(rnd)
+        cls <- fprf_CLASS_BFP32(result32)
+        result <- DOUBLE(result32)
+    else
+        rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
+        result <- bfp64_CONVERT_FROM_BFP(rnd)
+        cls <- fprf_CLASS_BFP64(result)
 
-        if xx_flag = 1 then SetFX(FPSCR.XX)
+    if xx_flag = 1 then SetFX(FPSCR.XX)
 
-        FRT <- result
-        FPSCR.FPRF <- cls
-        FPSCR.FR <- inc_flag
-        FPSCR.FI <- xx_flag
+    FRT <- result
+    FPSCR.FPRF <- cls
+    FPSCR.FR <- inc_flag
+    FPSCR.FI <- xx_flag
 ```
 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX,
 don't remove them -->