mips.mips.md (zero_extendsidi2): Do not allow SP to appear in operands[1] if it is...

	* config/mips.mips.md (zero_extendsidi2): Do not allow SP to appear
	in operands[1] if it is a MEM and TARGET_MIPS16 is active.
	(zero_extendsidi2_dext): Likewise.

From-SVN: r246924

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 33b094e56f5fd8dce95ee25e492588ca4bcc3380..788f02942cc444a6fe75d84963d442b387b2a064 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2017-04-13  Jeff Law  <law@redhat.com>
+
+       * config/mips.mips.md (zero_extendsidi2): Do not allow SP to appear
+       in operands[1] if it is a MEM and TARGET_MIPS16 is active.
+       (zero_extendsidi2_dext): Likewise.
+
 2017-04-13  Jakub Jelinek  <jakub@redhat.com>
 
        PR sanitizer/80403

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 7acf00d0451d82c906fb5a86ece521d3c9ee6fc6..dd5e1e77436f8880ea2f703a5f43aa7aef203256 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -3493,7 +3493,10 @@
 (define_insn_and_split "*zero_extendsidi2"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
-  "TARGET_64BIT && !ISA_HAS_EXT_INS"
+  "TARGET_64BIT && !ISA_HAS_EXT_INS
+   && !(TARGET_MIPS16
+        && MEM_P (operands[1])
+        && reg_mentioned_p (stack_pointer_rtx, operands[1]))"
   "@
    #
    lwu\t%0,%1"
@@ -3509,7 +3512,10 @@
 (define_insn "*zero_extendsidi2_dext"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
-  "TARGET_64BIT && ISA_HAS_EXT_INS"
+  "TARGET_64BIT && ISA_HAS_EXT_INS
+   && !(TARGET_MIPS16
+        && MEM_P (operands[1])
+        && reg_mentioned_p (stack_pointer_rtx, operands[1]))"
   "@
    dext\t%0,%1,0,32
    lwu\t%0,%1"