intel/fs: Use an explicit D type for vote any/all/eq intrinsics

The any/all intrinsics return a boolean value so D or UD is the correct
type.  Unfortunately, get_nir_dest has the annoying behavior of
returnning a float type by default.  This causes format conversion which
gives us -1.0f or 0.0f in the register.  If the consumer of the result
does an integer comparison to zero, it will give you the right boolean
value but if we do something more clever based on the 0/~0 assumption
for booleans, this will give the wrong value.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: mesa-stable@lists.freedesktop.org

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index dcd9942f369a6b7933d1282819990289cefcb892..3143bc6eea179ac9390f2d108cb8b54679a700b1 100644 (file)
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4207,6 +4207,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
          ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
       }
       bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ);
+
+      dest.type = BRW_REGISTER_TYPE_D;
       bld.MOV(dest, brw_imm_d(-1));
       set_predicate(dispatch_width == 8  ? BRW_PREDICATE_ALIGN1_ANY8H :
                     dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ANY16H :
@@ -4229,6 +4231,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
          ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
       }
       bld.CMP(bld.null_reg_d(), get_nir_src(instr->src[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ);
+
+      dest.type = BRW_REGISTER_TYPE_D;
       bld.MOV(dest, brw_imm_d(-1));
       set_predicate(dispatch_width == 8  ? BRW_PREDICATE_ALIGN1_ALL8H :
                     dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H :
@@ -4253,6 +4257,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
          ubld.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
       }
       bld.CMP(bld.null_reg_d(), value, uniformized, BRW_CONDITIONAL_Z);
+
+      dest.type = BRW_REGISTER_TYPE_D;
       bld.MOV(dest, brw_imm_d(-1));
       set_predicate(dispatch_width == 8  ? BRW_PREDICATE_ALIGN1_ALL8H :
                     dispatch_width == 16 ? BRW_PREDICATE_ALIGN1_ALL16H :