* bad trace:
-$I(s_0) P(s_0) \wedge T(s_0,s_1)\overline{I(s_1)}P(s_1)
-\wedge\dots\wedge T(s_{k-1},s_k)\overline{I(s_k)}
+$I(s_0) P(s_0) \wedge T(s_0,s_1)P(s_1)
+\wedge\dots\wedge T(s_{k-1},s_k)
\overline{P(s_k)}$
* k $\leftarrow$ 0
* base case: no path from initial state leads to a bad state in k steps
+* if base case fails, report the bad trace
* inductive case: no path ending in a bad state can be reached in k+1 steps
* if inductive case fails, $k \leftarrow k + 1$ and repeat
+* otherwise, proof is complete, circuit is safe.
# Single register with feedback
self.assertFormal(m, mode="prove", depth=5)
+
+
if __name__ == '__main__':
unittest.main()
```
![](test_enable.png)
+# Verifying memories with a "victim address"
+
+![](memory.png)
+
+# Verifying streams with transaction counters
+
+![](stream.png)
+
+# Dynamic SIMD
+
+```
+exp-a : ....0....0....0.... 1x 32-bit
+exp-a : ....0....0....1.... 1x 24-bit plus 1x 8-bit
+exp-a : ....0....1....0.... 2x 16-bit
+...
+...
+exp-a : ....1....1....0.... 2x 8-bit, 1x 16-bit
+exp-a : ....1....1....1.... 4x 8-bit
+```
+![](sum.png)
+
#
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