/* unsel module */
ddrphy_dly_sel_write(0);
+
+#ifdef ECP5DDRPHY
+ /* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
+ ddrphy_dly_sel_write(0xFF);
+ ddrphy_dly_sel_write(0);
+#endif
}
static void read_delay_inc(int module) {
/* unsel module */
ddrphy_dly_sel_write(0);
+
+#ifdef ECP5DDRPHY
+ /* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
+ ddrphy_dly_sel_write(0xFF);
+ ddrphy_dly_sel_write(0);
+#endif
}
static void read_bitslip_rst(char m)
printf("\n");
}
-#ifdef ECP5DDRPHY
- /* Toggle all dly_sel lines.
- * Which toggles all DQSBUFM.PAUSE lines, this ensures they're using the correct delays. */
- ddrphy_dly_sel_write(0xFF);
- ddrphy_dly_sel_write(0);
-#endif
return 1;
}