Add "add -mod"
authorClifford Wolf <clifford@clifford.at>
Fri, 20 Sep 2019 08:27:17 +0000 (10:27 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 20 Sep 2019 08:27:17 +0000 (10:27 +0200)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
passes/cmds/add.cc

index af6f7043d38b4a478d23c06245a478501460d997..dd05ac81f3125ff2a0c5c6ffa3c1140d79e6bc2b 100644 (file)
@@ -105,6 +105,11 @@ struct AddPass : public Pass {
                log("Like 'add -input', but also connect the signal between instances of the\n");
                log("selected modules.\n");
                log("\n");
+               log("\n");
+               log("    add -mod <name[s]>\n");
+               log("\n");
+               log("Add module[s] with the specified name[s].\n");
+               log("\n");
        }
        void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
        {
@@ -113,6 +118,7 @@ struct AddPass : public Pass {
                bool arg_flag_input = false;
                bool arg_flag_output = false;
                bool arg_flag_global = false;
+               bool mod_mode = false;
                int arg_width = 0;
 
                size_t argidx;
@@ -133,8 +139,20 @@ struct AddPass : public Pass {
                                arg_width = atoi(args[++argidx].c_str());
                                continue;
                        }
+                       if (arg == "-mod") {
+                               mod_mode = true;
+                               argidx++;
+                               break;
+                       }
                        break;
                }
+
+               if (mod_mode) {
+                       for (; argidx < args.size(); argidx++)
+                               design->addModule(RTLIL::escape_id(args[argidx]));
+                       return;
+               }
+
                extra_args(args, argidx, design);
 
                for (auto &mod : design->modules_)