soc/cores/liteeth_mini: add phy model for verilator simulation

diff --git a/litex/soc/cores/liteeth_mini/common.py b/litex/soc/cores/liteeth_mini/common.py
index 4638c76c208c7f742291995de5fd63b7d24b36e4..3f16e91cf78687127ab55287aa7b752bd4a5763e 100644 (file)
--- a/litex/soc/cores/liteeth_mini/common.py
+++ b/litex/soc/cores/liteeth_mini/common.py
@@ -1,8 +1,8 @@
 from migen import *
 from migen.genlib.record import *
 
-from misoc.interconnect.csr import *
-from misoc.interconnect.stream import *
+from litex.soc.interconnect.csr import *
+from litex.soc.interconnect.stream import *
 
 
 class Port:

diff --git a/litex/soc/cores/liteeth_mini/phy/__init__.py b/litex/soc/cores/liteeth_mini/phy/__init__.py
index a5d5ae92f2deef3cfdebe7462252af34139c9eee..8174a566d81366c0d7050939cc8bb442c4e1ce36 100644 (file)
--- a/litex/soc/cores/liteeth_mini/phy/__init__.py
+++ b/litex/soc/cores/liteeth_mini/phy/__init__.py
@@ -1,4 +1,4 @@
-from misoc.cores.liteeth_mini.common import *
+from litex.soc.cores.liteeth_mini.common import *
 
 
 def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
@@ -6,18 +6,18 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
     if hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
         if hasattr(clock_pads, "tx"):
             # This is a 10/100/1G PHY
-            from misoc.cores.liteeth_mini.phy.gmii_mii import LiteEthPHYGMIIMII
+            from litex.soc.cores.liteeth_mini.phy.gmii_mii import LiteEthPHYGMIIMII
             return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
         else:
             # This is a pure 1G PHY
-            from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMII
+            from litex.soc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMII
             return LiteEthPHYGMII(clock_pads, pads, **kwargs)
     elif hasattr(pads, "rx_ctl"):
         # This is a 10/100/1G RGMII PHY
         raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
     elif len(pads.tx_data) == 4:
         # This is a MII PHY
-        from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMII
+        from litex.soc.cores.liteeth_mini.phy.mii import LiteEthPHYMII
         return LiteEthPHYMII(clock_pads, pads, **kwargs)
     else:
         raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation")

diff --git a/litex/soc/cores/liteeth_mini/phy/gmii.py b/litex/soc/cores/liteeth_mini/phy/gmii.py
index bb3fc0bb9b877100e1d8b8fbb241d52bb24306cc..e73cc34135951595d6eee9886ce01cd1ccf9ec5f 100644 (file)
--- a/litex/soc/cores/liteeth_mini/phy/gmii.py
+++ b/litex/soc/cores/liteeth_mini/phy/gmii.py
@@ -2,7 +2,7 @@ from migen import *
 from migen.genlib.io import DDROutput
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from misoc.cores.liteeth_mini.common import *
+from litex.soc.cores.liteeth_mini.common import *
 
 
 class LiteEthPHYGMIITX(Module):

diff --git a/litex/soc/cores/liteeth_mini/phy/gmii_mii.py b/litex/soc/cores/liteeth_mini/phy/gmii_mii.py
index 6946c6c3d46785b7d6f281b4fe4c305966eabfcf..4ea06eeca57f9787971e110f8f07196548657d56 100644 (file)
--- a/litex/soc/cores/liteeth_mini/phy/gmii_mii.py
+++ b/litex/soc/cores/liteeth_mini/phy/gmii_mii.py
@@ -2,11 +2,11 @@ from migen import *
 from migen.genlib.io import DDROutput
 from migen.genlib.cdc import PulseSynchronizer
 
-from misoc.interconnect.stream import *
-from misoc.cores.liteeth_mini.common import *
-from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIICRG
-from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
-from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
+from litex.soc.interconnect.stream import *
+from litex.soc.cores.liteeth_mini.common import *
+from litex.soc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIICRG
+from litex.soc.cores.liteeth_mini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
+from litex.soc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
 
 
 modes = {

diff --git a/litex/soc/cores/liteeth_mini/phy/loopback.py b/litex/soc/cores/liteeth_mini/phy/loopback.py
index 28b1430ec1b38a5d677e2fce7c62c5e06fbe38e5..fd7583c6a78b5d2f8a94f774022c252373daec5e 100644 (file)
--- a/litex/soc/cores/liteeth_mini/phy/loopback.py
+++ b/litex/soc/cores/liteeth_mini/phy/loopback.py
@@ -1,9 +1,9 @@
 from migen import *
 
-from misoc.interconnect.csr import *
-from misoc.interconnect.stream import *
-from misoc.cores.liteeth_mini.common import *
-from misoc.cores.liteeth.mini.generic import *
+from litex.soc.interconnect.csr import *
+from litex.soc.interconnect.stream import *
+from litex.soc.cores.liteeth_mini.common import *
+from litex.soc.cores.liteeth.mini.generic import *
 
 
 class LiteEthPHYLoopbackCRG(Module, AutoCSR):

diff --git a/litex/soc/cores/liteeth_mini/phy/mii.py b/litex/soc/cores/liteeth_mini/phy/mii.py
index c5bf5271aa2e7f5ec2d9407f63460ea275ab4a66..5072091ad78977a25443815c5ffeaa7a40938927 100644 (file)
--- a/litex/soc/cores/liteeth_mini/phy/mii.py
+++ b/litex/soc/cores/liteeth_mini/phy/mii.py
@@ -1,8 +1,8 @@
 from migen import *
 
-from misoc.interconnect.csr import *
-from misoc.interconnect.stream import *
-from misoc.cores.liteeth_mini.common import *
+from litex.soc.interconnect.csr import *
+from litex.soc.interconnect.stream import *
+from litex.soc.cores.liteeth_mini.common import *
 
 
 def converter_description(dw):

diff --git a/litex/soc/cores/liteeth_mini/phy/model.py b/litex/soc/cores/liteeth_mini/phy/model.py
new file mode 100644 (file)
index 0000000..6deed17
--- /dev/null
+++ b/litex/soc/cores/liteeth_mini/phy/model.py
@@ -0,0 +1,58 @@
+import os
+
+from litex.soc.cores.liteeth_mini.common import *
+
+
+class LiteEthPHYModelCRG(Module, AutoCSR):
+    def __init__(self):
+        self._reset = CSRStorage()
+
+        # # #
+
+        self.clock_domains.cd_eth_rx = ClockDomain()
+        self.clock_domains.cd_eth_tx = ClockDomain()
+        self.comb += [
+            self.cd_eth_rx.clk.eq(ClockSignal()),
+            self.cd_eth_tx.clk.eq(ClockSignal())
+        ]
+
+        reset = self._reset.storage
+        self.comb += [
+            self.cd_eth_rx.rst.eq(reset),
+            self.cd_eth_tx.rst.eq(reset)
+        ]
+
+
+class LiteEthPHYModel(Module, AutoCSR):
+    def __init__(self, pads, tap="tap0", ip_address="192.168.0.14"):
+        self.dw = 8
+        self.submodules.crg = LiteEthPHYModelCRG()
+        self.sink = sink = Sink(eth_phy_description(8))
+        self.source = source = Source(eth_phy_description(8))
+        self.tap = tap
+        self.ip_address = ip_address
+
+        self.comb += [
+            pads.source_stb.eq(self.sink.stb),
+            pads.source_data.eq(self.sink.data),
+            self.sink.ack.eq(1)
+        ]
+
+        self.sync += [
+            self.source.stb.eq(pads.sink_stb),
+            self.source.sop.eq(pads.sink_stb & ~self.source.stb),
+            self.source.data.eq(pads.sink_data),
+        ]
+        self.comb += [
+            self.source.eop.eq(~pads.sink_stb & self.source.stb),
+        ]
+
+        # TODO avoid use of os.system
+        os.system("openvpn --mktun --dev {}".format(self.tap))
+        os.system("ifconfig {} {} up".format(self.tap, self.ip_address))
+        os.system("mknod /dev/net/{} c 10 200".format(self.tap))
+
+    def do_exit(self, *args, **kwargs):
+        # TODO avoid use of os.system
+        os.system("rm -f /dev/net/{}".format(self.tap))
+        os.system("openvpn --rmtun --dev {}".format(self.tap))

diff --git a/litex/soc/cores/liteeth_mini/phy/s6rgmii.py b/litex/soc/cores/liteeth_mini/phy/s6rgmii.py
index 1f312aceb549d256b2f8514916cb5601e99ed9d1..b2b2876a13ab6b5b986c41f0e546405bfd3d5500 100644 (file)
--- a/litex/soc/cores/liteeth_mini/phy/s6rgmii.py
+++ b/litex/soc/cores/liteeth_mini/phy/s6rgmii.py
@@ -5,9 +5,9 @@ from migen.genlib.io import DDROutput
 from migen.genlib.misc import WaitTimer
 from migen.genlib.fsm import FSM, NextState
 
-from misoc.interconnect.stream import *
-from misoc.interconnect.csr import *
-from misoc.cores.liteeth_mini.common import *
+from litex.soc.interconnect.stream import *
+from litex.soc.interconnect.csr import *
+from litex.soc.cores.liteeth_mini.common import *
 
 
 class LiteEthPHYRGMIITX(Module):