add BUFIO to clockgen buffer options

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 3d427bcffd698ec6e2489c2fa020841021dbed99..5e62f5de75eb51add0425441c01d4e271ca3d7e4 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -59,6 +59,8 @@ class XilinxClocking(Module, AutoCSR):
                 self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf)
             elif buf == "bufgce" and clk_ce != None:
                 self.specials += Instance("BUFGCE", i_I=clkout, o_O=clkout_buf, i_CE=clk_ce)
+            elif buf == "bufio":
+                self.specials += Instance("BUFIO", i_I=clkout, o_O=clkout_buf)
             else:
                 raise ValueError