radv/gfx10: set MAX_ALLOC_COUNT
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 25 Jun 2019 06:29:24 +0000 (08:29 +0200)
committerBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Sun, 7 Jul 2019 15:03:38 +0000 (17:03 +0200)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/si_cmd_buffer.c

index 52cb7477c08dbf4b0270b4b968e3b5345ff87c53..57e143ece46eca22ced8471f134f936ed4c66b8d 100644 (file)
@@ -321,6 +321,7 @@ si_emit_graphics(struct radv_physical_device *physical_device,
        if (physical_device->rad_info.chip_class >= GFX9) {
                unsigned num_se = physical_device->rad_info.max_se;
                unsigned pc_lines = 0;
+               unsigned max_alloc_count = 0;
 
                switch (physical_device->rad_info.family) {
                case CHIP_VEGA10:
@@ -330,14 +331,25 @@ si_emit_graphics(struct radv_physical_device *physical_device,
                        break;
                case CHIP_RAVEN:
                case CHIP_RAVEN2:
+               case CHIP_NAVI10:
+               case CHIP_NAVI12:
                        pc_lines = 1024;
                        break;
+               case CHIP_NAVI14:
+                       pc_lines = 512;
+                       break;
                default:
                        assert(0);
                }
 
+               if (physical_device->rad_info.chip_class >= GFX10) {
+                       max_alloc_count = pc_lines / 3;
+               } else {
+                       max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
+               }
+
                radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
-                                      S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
+                                      S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
                                       S_028C48_MAX_PRIM_PER_BATCH(1023));
                radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
                                       S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));