Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index c96e0d8f16d654bd8e464bb1d696b99ee8857805..0c8f282a4fd5a032142444801d801430514de42b 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -53,15 +53,15 @@ module BUFGCTRL(
     input CE0, input CE1,
     input IGNORE0, input IGNORE1);
 
-parameter INIT_OUT = 0;
-parameter PRESELECT_I0 = 0;
-parameter PRESELECT_I1 = 0;
-parameter IS_CE0_INVERTED = 0;
-parameter IS_CE1_INVERTED = 0;
-parameter IS_S0_INVERTED = 0;
-parameter IS_S1_INVERTED = 0;
-parameter IS_IGNORE0_INVERTED = 0;
-parameter IS_IGNORE1_INVERTED = 0;
+parameter [0:0] INIT_OUT = 1'b0;
+parameter PRESELECT_I0 = "FALSE";
+parameter PRESELECT_I1 = "FALSE";
+parameter [0:0] IS_CE0_INVERTED = 1'b0;
+parameter [0:0] IS_CE1_INVERTED = 1'b0;
+parameter [0:0] IS_S0_INVERTED = 1'b0;
+parameter [0:0] IS_S1_INVERTED = 1'b0;
+parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
+parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
 
 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
@@ -74,9 +74,9 @@ endmodule
 
 module BUFHCE(output O, input I, input CE);
 
-parameter INIT_OUT = 0;
+parameter [0:0] INIT_OUT = 1'b0;
 parameter CE_TYPE = "SYNC";
-parameter IS_CE_INVERTED = 0;
+parameter [0:0] IS_CE_INVERTED = 1'b0;
 
 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
 

diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index 56520ea1065ea72a0d4d89ee408b12db9b670073..8b06c31551ae2ec7517ef661997dd22b65d48237 100644 (file)
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -28,12 +28,12 @@ function xtract_cell_decl()
        # xtract_cell_decl BUFG
        xtract_cell_decl BUFGCE
        xtract_cell_decl BUFGCE_1
-       xtract_cell_decl BUFGCTRL
+       #xtract_cell_decl BUFGCTRL
        xtract_cell_decl BUFGMUX
        xtract_cell_decl BUFGMUX_1
        xtract_cell_decl BUFGMUX_CTRL
        xtract_cell_decl BUFH
-       xtract_cell_decl BUFHCE
+       #xtract_cell_decl BUFHCE
        xtract_cell_decl BUFIO
        xtract_cell_decl BUFMR
        xtract_cell_decl BUFMRCE
@@ -92,7 +92,7 @@ function xtract_cell_decl()
        # xtract_cell_decl LUT4
        # xtract_cell_decl LUT5
        # xtract_cell_decl LUT6
-       xtract_cell_decl LUT6_2
+       #xtract_cell_decl LUT6_2
        xtract_cell_decl MMCME2_ADV
        xtract_cell_decl MMCME2_BASE
        # xtract_cell_decl MUXF7

diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 497518d35033e313138ef3708fb47522542cca47..4fb6798bede9681718ab051d4d122dd2a1fcb8e8 100644 (file)
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -30,29 +30,6 @@ module BUFGCE_1 (...);
     input CE, I;
 endmodule
 
-module BUFGCTRL (...);
-    output O;
-    input CE0;
-    input CE1;
-    input I0;
-    input I1;
-    input IGNORE0;
-    input IGNORE1;
-    input S0;
-    input S1;
-    parameter integer INIT_OUT = 0;
-    parameter PRESELECT_I0 = "FALSE";
-    parameter PRESELECT_I1 = "FALSE";
-    parameter [0:0] IS_CE0_INVERTED = 1'b0;
-    parameter [0:0] IS_CE1_INVERTED = 1'b0;
-    parameter [0:0] IS_I0_INVERTED = 1'b0;
-    parameter [0:0] IS_I1_INVERTED = 1'b0;
-    parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
-    parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
-    parameter [0:0] IS_S0_INVERTED = 1'b0;
-    parameter [0:0] IS_S1_INVERTED = 1'b0;
-endmodule
-
 module BUFGMUX (...);
     parameter CLK_SEL_TYPE = "SYNC";
     output O;
@@ -77,15 +54,6 @@ module BUFH (...);
     input I;
 endmodule
 
-module BUFHCE (...);
-    parameter CE_TYPE = "SYNC";
-    parameter integer INIT_OUT = 0;
-    parameter [0:0] IS_CE_INVERTED = 1'b0;
-    output O;
-    input CE;
-    input I;
-endmodule
-
 module BUFIO (...);
     output O;
     input I;
@@ -2420,12 +2388,6 @@ module LDPE (...);
     input D, G, GE, PRE;
 endmodule
 
-module LUT6_2 (...);
-    parameter [63:0] INIT = 64'h0000000000000000;
-    input I0, I1, I2, I3, I4, I5;
-    output O5, O6;
-endmodule
-
 module MMCME2_ADV (...);
     parameter BANDWIDTH = "OPTIMIZED";
     parameter real CLKFBOUT_MULT_F = 5.000;