serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index ab73cea22ed5e297785782759c576433f1b6062b..e24853c4a7227824aff67360b8393873e2a8856f 100644 (file)
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -88,4 +88,4 @@ class SERV(CPU):
 
     def do_finalize(self):
         assert hasattr(self, "reset_address")
-        self.specials += Instance("serv_top", **self.cpu_params)
+        self.specials += Instance("serv_rf_top", **self.cpu_params)