(no commit message)

diff --git a/Harmonised_RVV/Packed_SIMD.mdwn b/Harmonised_RVV/Packed_SIMD.mdwn
index 03d61dfa423af656f7f4a8aa264b3464d39e7aee..b863b5f981be0dce0e8e19068dbee2ee2f8f1216 100644 (file)
--- a/Harmonised_RVV/Packed_SIMD.mdwn
+++ b/Harmonised_RVV/Packed_SIMD.mdwn
@@ -37,7 +37,7 @@ However, note RV32I registers can fit 4x INT8 elements.  To preserve Andes SIMD
 
 ##### Alternative register "banks" and alternative MVL
 
-A programmer can configure VCFG with the any mix of these alternative configurations:
+A programmer can configure VCFG with any mix of these alternative configurations:
 
 *  v0-v31 are all INT 16, and MVL is same as for Default MVL above
 *  v0-v31 are all INT 8 and MVL is 4 on RV32I and 8 on RV64I