(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 25120e3abed0f4ec6c2b46767e244c263b6e5cdd..bba4610807b8d70262d739de62d9fcc16291ad41 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -238,7 +238,7 @@ form.
 
 # Major opcodes summary <a name="major_op_summary"> </a>
 
-Simple-V itself only requires five instructions with 6-bit Minor XO
+Simple-V itself only requires six instructions with 6-bit Minor XO
 (bits 26-31), and the SVP64 Prefix Encoding requires
 25% space of the EXT001 Major Opcode.
 There are **no** Vector Instructions and consequently **no further
@@ -329,7 +329,7 @@ intended for mass-volume product deployment. Every in-good-faith effort will
 therefore be made to work with the OPF ISA WG to
 submit SVP64 via the External RFC Process.
 
-**Whilst SVP64 is only 5 instructions
+**Whilst SVP64 is only 6 instructions
 the heavy focus on VSX for the past 12 years has left the SFFS Level
 anaemic and out-of-date compared to ARM and x86.**
 This is very much