is `O(N^2)`) this in turn means that the estimate has to be computed
from a *128* bit dividend and a 64-bit divisor. Such an operation
simply does not exist in most Scalar 64-bit ISAs. Although Power ISA
-comes close with `divdeu`, by placing the dividend in the upper half
-of a 128-bit computation, the lower half is zero. Again Power ISA
+comes close with `divdeu`, by placing one operand in the upper half
+of a 128-bit dividend, the lower half is zero. Again Power ISA
has a Packed SIMD instruction `vdivuq` which is a 128/128
(quad) divide, not a 128/64, and its use would require considerable
effort to move registers to and from GPRs. Some investigation into