RISC-V: Fix -fsignaling-nans for glibc testsuite.

	gcc/
	* config/riscv/riscv.md (f<quiet_pattern>_quiet<ANYF:mode><X:mode>4):
	Add define_expand.  Add ! HONOR_SNANS check to current pattern.  Add
	new pattern using HONOR_SNANS that emits one extra instruction.

Co-Authored-By: Jim Wilson <jimw@sifive.com>
From-SVN: r264892

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8d754af220144acc15d5bdc4c9d8510f88b4c8e3..6d81f73a708e5deec15857f14a2f5335b0745c54 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2018-10-05  Andrew Waterman  <andrew@sifive.com>
+           Jim Wilson  <jimw@sifive.com>
+
+       * config/riscv/riscv.md (f<quiet_pattern>_quiet<ANYF:mode><X:mode>4):
+       Add define_expand.  Add ! HONOR_SNANS check to current pattern.  Add
+       new pattern using HONOR_SNANS that emits one extra instruction.
+
 2018-10-05  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/rs6000.md (unnamed mfcr scc_comparison_operator

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4162dc578e8a606436154e165b934247276d0cd9..b6c20230ffdf203634d102d5da99c66b41ebc92a 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1957,19 +1957,41 @@
   [(set_attr "type" "fcmp")
    (set_attr "mode" "<UNITMODE>")])
 
-(define_insn "f<quiet_pattern>_quiet<ANYF:mode><X:mode>4"
-   [(set (match_operand:X         0 "register_operand" "=r")
+(define_expand "f<quiet_pattern>_quiet<ANYF:mode><X:mode>4"
+   [(parallel [(set (match_operand:X      0 "register_operand")
+                   (unspec:X
+                    [(match_operand:ANYF 1 "register_operand")
+                     (match_operand:ANYF 2 "register_operand")]
+                    QUIET_COMPARISON))
+              (clobber (match_scratch:X 3))])]
+  "TARGET_HARD_FLOAT")
+
+(define_insn "*f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_default"
+   [(set (match_operand:X      0 "register_operand" "=r")
         (unspec:X
-            [(match_operand:ANYF 1 "register_operand" " f")
-             (match_operand:ANYF 2 "register_operand" " f")]
-            QUIET_COMPARISON))
+         [(match_operand:ANYF 1 "register_operand" " f")
+          (match_operand:ANYF 2 "register_operand" " f")]
+         QUIET_COMPARISON))
     (clobber (match_scratch:X 3 "=&r"))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT && ! HONOR_SNANS (<ANYF:MODE>mode)"
   "frflags\t%3\n\tf<quiet_pattern>.<fmt>\t%0,%1,%2\n\tfsflags %3"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "<UNITMODE>")
    (set (attr "length") (const_int 12))])
 
+(define_insn "*f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_snan"
+   [(set (match_operand:X      0 "register_operand" "=r")
+        (unspec:X
+         [(match_operand:ANYF 1 "register_operand" " f")
+          (match_operand:ANYF 2 "register_operand" " f")]
+         QUIET_COMPARISON))
+    (clobber (match_scratch:X 3 "=&r"))]
+  "TARGET_HARD_FLOAT && HONOR_SNANS (<ANYF:MODE>mode)"
+  "frflags\t%3\n\tf<quiet_pattern>.<fmt>\t%0,%1,%2\n\tfsflags %3\n\tfeq.<fmt>\tzero,%1,%2"
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "<UNITMODE>")
+   (set (attr "length") (const_int 16))])
+
 (define_insn "*seq_zero_<X:mode><GPR:mode>"
   [(set (match_operand:GPR       0 "register_operand" "=r")
        (eq:GPR (match_operand:X 1 "register_operand" " r")