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Make sstatus.MXR readable
author
Andrew Waterman
<andrew@sifive.com>
Tue, 31 Jul 2018 18:26:47 +0000
(11:26 -0700)
committer
Andrew Waterman
<andrew@sifive.com>
Tue, 31 Jul 2018 18:27:22 +0000
(11:27 -0700)
h/t @taoliug
riscv/processor.cc
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diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index 52f69c1d460778519bf34f8020c4c6b73b9dd3cb..2a4a18c5a78b1adce8514fb95f98a7dfba3e2b8f 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-584,7
+584,7
@@
reg_t processor_t::get_csr(int which)
case CSR_MCOUNTEREN: return state.mcounteren;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
- | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
+ | SSTATUS_XS | SSTATUS_SUM | SSTATUS_
MXR | SSTATUS_
UXL;
reg_t sstatus = state.mstatus & mask;
if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
(sstatus & SSTATUS_XS) == SSTATUS_XS)