r600g: don't add PA_SC_LINE_STIPPLE to rasterizer_state
authorMarek Olšák <maraeo@gmail.com>
Sun, 29 Jan 2012 04:22:00 +0000 (05:22 +0100)
committerMarek Olšák <maraeo@gmail.com>
Tue, 31 Jan 2012 01:17:56 +0000 (02:17 +0100)
It's always emitted in draw_vbo.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600_pipe.h
src/gallium/drivers/r600/r600_state.c
src/gallium/drivers/r600/r600_state_common.c

index 9f9a6a131304da120fd4bd06ef78dfc7c77b33de..a5a443c2b1cdb9b5797209679a9bfd539d65e808 100644 (file)
@@ -889,6 +889,9 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
        rs->sprite_coord_enable = state->sprite_coord_enable;
        rs->two_side = state->light_twoside;
        rs->clip_plane_enable = state->clip_plane_enable;
+       rs->pa_sc_line_stipple = state->line_stipple_enable ?
+                               S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
+                               S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 
        clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 
@@ -946,14 +949,6 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
 
        tmp = (unsigned)state->line_width * 8;
        r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
-
-       if (state->line_stipple_enable) {
-               r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
-                                       S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
-                                       S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
-                                       0x9FFFFFFF, NULL, 0);
-       }
-
        r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
                                S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
                                0xFFFFFFFF, NULL, 0);
index b7c5e55b5405c4350b0321106ae513ff71088ec2..d4578bd93db316d8c6173ebf276536ec5dc103b2 100644 (file)
@@ -109,6 +109,7 @@ struct r600_pipe_rasterizer {
        boolean                         two_side;
        unsigned                        sprite_coord_enable;
        unsigned                        clip_plane_enable;
+       unsigned                        pa_sc_line_stipple;
        float                           offset_units;
        float                           offset_scale;
 };
@@ -209,6 +210,7 @@ struct r600_pipe_context {
        struct pipe_framebuffer_state   framebuffer;
        unsigned                        cb_target_mask;
        unsigned                        cb_color_control;
+       unsigned                        pa_sc_line_stipple;
        /* for saving when using blitter */
        struct pipe_stencil_ref         stencil_ref;
        struct pipe_viewport_state      viewport;
index e1d8ab3afc5613c1739f5124785738f44dc8699b..ae9f797e1e27260306c74c091c09b155faa7c213 100644 (file)
@@ -943,6 +943,9 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
        rs->sprite_coord_enable = state->sprite_coord_enable;
        rs->two_side = state->light_twoside;
        rs->clip_plane_enable = state->clip_plane_enable;
+       rs->pa_sc_line_stipple = state->line_stipple_enable ?
+                               S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
+                               S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 
        clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
        /* offset */
@@ -1000,13 +1003,6 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
        tmp = (unsigned)state->line_width * 8;
        r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL, 0);
 
-       if (state->line_stipple_enable) {
-               r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE,
-                                       S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
-                                       S_028A0C_REPEAT_COUNT(state->line_stipple_factor),
-                                       0x9FFFFFFF, NULL, 0);
-       }
-
        if (rctx->chip_class >= R700)
                sc_mode_cntl = 0x514002;
        else
index 9833de0f5222963a0c25b511021e51a40c85d7a9..84ccd5e9c80f11e8da3596821e1dac360b0a2d46 100644 (file)
@@ -166,6 +166,7 @@ void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 
        rctx->sprite_coord_enable = rs->sprite_coord_enable;
        rctx->two_side = rs->two_side;
+       rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 
        rctx->rasterizer = rs;
 
@@ -752,9 +753,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
                r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, 0xFFFFFFFF, NULL, 0);
                r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0);
                r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, 0xFFFFFFFF, NULL, 0);
-               r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE,
-                                       0,
-                                       S_028A0C_AUTO_RESET_CNTL(3), NULL, 0);
+               r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0xFFFFFFFF, NULL, 0);
                r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL,
                                        0,
                                        S_028814_PROVOKING_VTX_LAST(1), NULL, 0);
@@ -777,7 +776,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
                ls_mask = 1;
        else if (prim == V_008958_DI_PT_LINESTRIP) 
                ls_mask = 2;
-       r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask));
+       r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 
        if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
                r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1));