uart: generate ack for rx (serialboot OK with sim)

diff --git a/misoclib/com/uart/__init__.py b/misoclib/com/uart/__init__.py
index 8d566fb6b59aa69043187864ea8bc24bd84c1fb6..a07462a71dbeadfd894bdd12ce8de469c8328d9a 100644 (file)
--- a/misoclib/com/uart/__init__.py
+++ b/misoclib/com/uart/__init__.py
@@ -26,5 +26,6 @@ class UART(Module, AutoCSR):
                ]
                self.comb += [
                        self.ev.tx.trigger.eq(phy.sink.stb & phy.sink.ack),
-                       self.ev.rx.trigger.eq(phy.source.stb) #phy.source.ack supposed to be always 1
+                       self.ev.rx.trigger.eq(phy.source.stb & phy.source.ack),
+                       phy.source.ack.eq(~self.ev.rx.pending)
                ]

diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py
index 2879b2cb2de9454274703b34dedee9a9487eaaa6..4682a53f65d01042d3e2e3530f70a1be7ce76e53 100644 (file)
--- a/misoclib/com/uart/phy/sim.py
+++ b/misoclib/com/uart/phy/sim.py
@@ -12,5 +12,6 @@ class UARTPHYSim(Module):
                        self.sink.ack.eq(pads.source_ack),
 
                        self.source.stb.eq(pads.sink_stb),
-                       self.source.data.eq(pads.sink_data)
+                       self.source.data.eq(pads.sink_data),
+                       pads.sink_ack.eq(self.source.ack)
                ]