platforms/minispartan6: fix IOStandard/Slew, add FpgaProg programmer, change default...

diff --git a/mibuild/platforms/minispartan6.py b/mibuild/platforms/minispartan6.py
index baff130aa8918d9c0d2bb58ac2820f74b4bbf50a..5f82723e15f1dea94cf3536a26dd139edf1a8d35 100644 (file)
--- a/mibuild/platforms/minispartan6.py
+++ b/mibuild/platforms/minispartan6.py
@@ -4,51 +4,51 @@
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
 from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx.programmer import XC3SProg
+from mibuild.xilinx.programmer import XC3SProg, FpgaProg
 
 _io = [
-       ("user_led", 0, Pins("P11"), IOStandard("LVTTL"), Misc("SLEW=SLOW")),
-       ("user_led", 1, Pins("N9"),  IOStandard("LVTTL"), Misc("SLEW=SLOW")),
-       ("user_led", 2, Pins("M9"),  IOStandard("LVTTL"), Misc("SLEW=SLOW")),
-       ("user_led", 3, Pins("P9"),  IOStandard("LVTTL"), Misc("SLEW=SLOW")),
-       ("user_led", 4, Pins("T8"),  IOStandard("LVTTL"), Misc("SLEW=SLOW")),
-       ("user_led", 5, Pins("N8"),  IOStandard("LVTTL"), Misc("SLEW=SLOW")),
-       ("user_led", 6, Pins("P8"),  IOStandard("LVTTL"), Misc("SLEW=SLOW")),
-       ("user_led", 7, Pins("P7"),  IOStandard("LVTTL"), Misc("SLEW=SLOW")),
-
-       ("user_sw", 0, Pins("L1"), IOStandard("LVTTL"), Misc("PULLUP")),
-       ("user_sw", 1, Pins("L3"), IOStandard("LVTTL"), Misc("PULLUP")),
-       ("user_sw", 2, Pins("L4"), IOStandard("LVTTL"), Misc("PULLUP")),
-       ("user_sw", 3, Pins("L5"), IOStandard("LVTTL"), Misc("PULLUP")),
+       ("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")),
+       ("user_led", 1, Pins("N9"),  IOStandard("LVCMOS33")),
+       ("user_led", 2, Pins("M9"),  IOStandard("LVCMOS33")),
+       ("user_led", 3, Pins("P9"),  IOStandard("LVCMOS33")),
+       ("user_led", 4, Pins("T8"),  IOStandard("LVCMOS33")),
+       ("user_led", 5, Pins("N8"),  IOStandard("LVCMOS33")),
+       ("user_led", 6, Pins("P8"),  IOStandard("LVCMOS33")),
+       ("user_led", 7, Pins("P7"),  IOStandard("LVCMOS33")),
+
+       ("user_sw", 0, Pins("L1"), IOStandard("LVCMOS33"), Misc("PULLUP")),
+       ("user_sw", 1, Pins("L3"), IOStandard("LVCMOS33"), Misc("PULLUP")),
+       ("user_sw", 2, Pins("L4"), IOStandard("LVCMOS33"), Misc("PULLUP")),
+       ("user_sw", 3, Pins("L5"), IOStandard("LVCMOS33"), Misc("PULLUP")),
 
        ("clk32", 0, Pins("J4"), IOStandard("LVCMOS33")),
        ("clk50", 0, Pins("K3"), IOStandard("LVCMOS33")),
 
        ("spiflash", 0,
-               Subsignal("cs_n", Pins("T3"), IOStandard("LVTTL")),
-               Subsignal("clk",  Pins("R11"), IOStandard("LVTTL")),
-               Subsignal("mosi", Pins("T10"), IOStandard("LVTTL")),
-               Subsignal("miso", Pins("P10"), IOStandard("LVTTL"))
+               Subsignal("cs_n", Pins("T3"), IOStandard("LVCMOS33")),
+               Subsignal("clk",  Pins("R11"), IOStandard("LVCMOS33")),
+               Subsignal("mosi", Pins("T10"), IOStandard("LVCMOS33")),
+               Subsignal("miso", Pins("P10"), IOStandard("LVCMOS33"))
        ),
 
        ("adc", 0,
-               Subsignal("cs_n", Pins("F6"), IOStandard("LVTTL")),
-               Subsignal("clk",  Pins("G6"), IOStandard("LVTTL")),
-               Subsignal("mosi", Pins("H4"), IOStandard("LVTTL")),
-               Subsignal("miso", Pins("H5"), IOStandard("LVTTL"))
+               Subsignal("cs_n", Pins("F6"), IOStandard("LVCMOS33")),
+               Subsignal("clk",  Pins("G6"), IOStandard("LVCMOS33")),
+               Subsignal("mosi", Pins("H4"), IOStandard("LVCMOS33")),
+               Subsignal("miso", Pins("H5"), IOStandard("LVCMOS33"))
        ),
 
        ("serial", 0,
-               Subsignal("tx", Pins("N6"), IOStandard("LVTTL")), # FTDI D1
-               Subsignal("rx", Pins("M7"), IOStandard("LVTTL"))  # FTDI D0
+               Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1
+               Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33"))  # FTDI D0
        ),
 
        ("audio", 0,
-               Subsignal("a0", Pins("B8"), IOStandard("LVTTL")),
-               Subsignal("a1", Pins("A8"), IOStandard("LVTTL"))
+               Subsignal("a0", Pins("B8"), IOStandard("LVCMOS33")),
+               Subsignal("a1", Pins("A8"), IOStandard("LVCMOS33"))
        ),
 
-       ("sdram_clock", 0, Pins("G16"), IOStandard("LVTTL")),
+       ("sdram_clock", 0, Pins("G16"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
        ("sdram", 0,
                Subsignal("a", Pins("T15 R16 P15 P16 N16 M15 M16 L16 K15 K16 R15 J16 H15")),
                Subsignal("dq", Pins("T13 T12 R12 T9 R9 T7 R7 T6 F16 E15 E16 D16 B16 B15 C16 C15")),
@@ -58,7 +58,8 @@ _io = [
                Subsignal("cs_n", Pins("R1")),
                Subsignal("cke", Pins("H16")),
                Subsignal("ba", Pins("R14 T14")),
-               Subsignal("dm", Pins("T5 F15"))
+               Subsignal("dm", Pins("T5 F15")),
+               IOStandard("LVCMOS33"), Misc("SLEW=FAST")
        ),
 
        ("sd", 0,
@@ -67,7 +68,8 @@ _io = [
                Subsignal("d", Pins("M10")),
                Subsignal("d1", Pins("L10")),
                Subsignal("d2", Pins("J11")),
-               Subsignal("cmd", Pins("K11"))
+               Subsignal("cmd", Pins("K11")),
+               IOStandard("LVCMOS33")
        ),
 
        ("dvi_in", 0,
@@ -75,8 +77,8 @@ _io = [
                Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")),
                Subsignal("data_p", Pins("C7 B6 B5"), IOStandard("TMDS_33")),
                Subsignal("data_n", Pins("A7 A6 A5"), IOStandard("TMDS_33")),
-               Subsignal("scl", Pins("C1"), IOStandard("LVTTL")),
-               Subsignal("sda", Pins("B1"), IOStandard("LVTTL"))
+               Subsignal("scl", Pins("C1"), IOStandard("LVCMOS33")),
+               Subsignal("sda", Pins("B1"), IOStandard("LVCMOS33"))
        ),
 
        ("dvi_out", 0,
@@ -97,11 +99,17 @@ _connectors = [
 ]
 
 class Platform(XilinxPlatform):
-       default_clk_name = "clk50"
-       default_clk_period = 20
+       default_clk_name = "clk32"
+       default_clk_period = 31.25
 
-       def __init__(self, device="xc6slx9"):
+       def __init__(self, device="xc6slx9", programmer="xc3sprog"):
+               self.programmer = programmer
                XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
 
        def create_programmer(self):
-               return XC3SProg("minispartan6", "bscan_spi_minispartan6.bit")
+               if self.programmer == "xc3sprog":
+                       return XC3SProg("minispartan6", "bscan_spi_minispartan6.bit")
+               elif self.programmer == "fpgaprog":
+                       return FpgaProg()
+               else:
+                       raise ValueError("{} programmer is not supported".format(programmer))