("d", 8)
]
-class FtdiPipe:
+class LiteUSBPipe:
def __init__(self, layout):
self.sink = Sink(layout)
self.source = Source(layout)
-class FtdiTimeout(Module):
+class LiteUSBTimeout(Module):
def __init__(self, clk_freq, length):
cnt_max = int(clk_freq*length)
width = bits_for(cnt_max)
-from misoclib.com.liteusb.frontend.uart import FtdiUART
-from misoclib.com.liteusb.frontend.dma import FtdiDMA
-from misoclib.com.liteusb.core.com import FtdiCom
-from misoclib.com.liteusb.core.crc import FtdiCRC32
+from misoclib.com.liteusb.frontend.uart import LiteUSBUART
+from misoclib.com.liteusb.frontend.dma import LiteUSBDMA
+from misoclib.com.liteusb.core.com import LiteUSBCom
+from misoclib.com.liteusb.core.crc import LiteUSBCRC32
from migen.flow.actor import *
from misoclib.com.liteusb.common import *
-from misoclib.com.liteusb.frontend.crossbar import FtdiCrossbar
-from misoclib.com.liteusb.core.packetizer import FtdiPacketizer
-from misoclib.com.liteusb.core.depacketizer import FtdiDepacketizer
-from misoclib.com.liteusb.phy.ft2232h import FtdiPHY
+from misoclib.com.liteusb.frontend.crossbar import LiteUSBCrossbar
+from misoclib.com.liteusb.core.packetizer import LiteUSBPacketizer
+from misoclib.com.liteusb.core.depacketizer import LiteUSBDepacketizer
-class FtdiCom(Module):
- def __init__(self, pads, *ports):
+class LiteUSBCom(Module):
+ def __init__(self, phy, *ports):
# crossbar
- self.submodules.crossbar = FtdiCrossbar(list(ports))
+ self.submodules.crossbar = LiteUSBCrossbar(list(ports))
# packetizer / depacketizer
- self.submodules.packetizer = FtdiPacketizer()
- self.submodules.depacketizer = FtdiDepacketizer()
+ self.submodules.packetizer = LiteUSBPacketizer()
+ self.submodules.depacketizer = LiteUSBDepacketizer()
self.comb += [
self.crossbar.slave.source.connect(self.packetizer.sink),
self.depacketizer.source.connect(self.crossbar.slave.sink)
]
# phy
- self.submodules.phy = FtdiPHY(pads)
self.comb += [
- self.packetizer.source.connect(self.phy.sink),
- self.phy.source.connect(self.depacketizer.sink)
+ self.packetizer.source.connect(phy.sink),
+ phy.source.connect(self.depacketizer.sink)
]
def __init__(self, layout):
CRCChecker.__init__(self, CRC32, layout)
-class FtdiCRC32(Module):
+class LiteUSBCRC32(Module):
def __init__(self, tag):
self.tag = tag
from misoclib.com.liteusb.common import *
-class FtdiDepacketizer(Module):
+class LiteUSBDepacketizer(Module):
def __init__(self, timeout=10):
self.sink = sink = Sink(phy_layout)
self.source = source = Source(user_layout)
header_pack.source.ack.eq(1),
)
- self.submodules.timeout = FtdiTimeout(60000000, timeout)
+ self.submodules.timeout = LiteUSBTimeout(60000000, timeout)
self.comb += self.timeout.clear.eq(fsm.ongoing("WAIT_SOP"))
fsm.act("RECEIVE_HEADER",
class TB(Module):
def __init__(self):
self.submodules.source = DepacketizerSourceModel(src_data)
- self.submodules.dut = FtdiDepacketizer()
+ self.submodules.dut = LiteUSBDepacketizer()
self.submodules.sink = DepacketizerSinkModel()
self.comb += [
from misoclib.com.liteusb.common import *
-class FtdiPacketizer(Module):
+class LiteUSBPacketizer(Module):
def __init__(self):
self.sink = sink = Sink(user_layout)
self.source = source = Source(phy_layout)
class TB(Module):
def __init__(self):
self.submodules.source = PacketizerSourceModel(src_data)
- self.submodules.dut = FtdiPacketizer()
+ self.submodules.dut = LiteUSBPacketizer()
self.submodules.sink = PacketizerSinkModel()
self.comb +=[
from misoclib.com.liteusb.common import *
-class FtdiCrossbar(Module):
+class LiteUSBCrossbar(Module):
def __init__(self, masters, slave=None):
if slave is None:
- slave = FtdiPipe(user_layout)
+ slave = LiteUSBPipe(user_layout)
self.slave = slave
# masters --> slave arbitration
from misoclib.com.liteusb.common import *
-class FtdiDMAWriter(Module, AutoCSR):
+class LiteUSBDMAWriter(Module, AutoCSR):
def __init__(self, lasmim):
self.sink = sink = Sink(user_layout)
self._crc_failed.status.eq(sink.error)
)
-class FtdiDMAReader(Module, AutoCSR):
+class LiteUSBDMAReader(Module, AutoCSR):
def __init__(self, lasmim, tag):
self.source = source = Source(user_layout)
self.ev.finalize()
self.comb += self.ev.done.trigger.eq(source.stb & source.eop)
-class FtdiDMA(Module, AutoCSR):
+class LiteUSBDMA(Module, AutoCSR):
def __init__(self, lasmim_ftdi_dma_wr, lasmim_ftdi_dma_rd, tag):
self.tag = tag
- self.submodules.writer = FtdiDMAWriter(lasmim_ftdi_dma_wr)
- self.submodules.reader = FtdiDMAReader(lasmim_ftdi_dma_rd, self.tag)
+ self.submodules.writer = LiteUSBDMAWriter(lasmim_ftdi_dma_wr)
+ self.submodules.reader = LiteUSBDMAReader(lasmim_ftdi_dma_rd, self.tag)
self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)
self.sink = self.writer.sink
from misoclib.com.liteusb.common import *
-class FtdiUART(Module, AutoCSR):
+class LiteUSBUART(Module, AutoCSR):
def __init__(self, tag, fifo_depth=64):
self.tag = tag
from misoclib.com.liteusb.common import *
-class FtdiPHY(Module):
+class FT2232HPHY(Module):
def __init__(self, pads, fifo_depth=32, read_time=16, write_time=16):
dw = flen(pads.data)
#
# TB
#
-class FtdiModel(Module, RandRun):
+class FT2232HModel(Module, RandRun):
def __init__(self, rd_data):
RandRun.__init__(self, 50)
self.rd_data = [0] + rd_data
class TB(Module):
def __init__(self):
- self.submodules.model = FtdiModel(model_rd_data)
- self.submodules.phy = FtdiPHY(self.model)
+ self.submodules.model = FT2232HModel(model_rd_data)
+ self.submodules.phy = FT2232HPHY(self.model)
self.submodules.user = UserModel(user_wr_data)
#print(len(tb.user.rd_data))
#print(len(tb.model.wr_data))
- print_results("FtdiModel --> UserModel", model_rd_data, tb.user.rd_data)
- print_results("UserModel --> FtdiModel", user_wr_data, tb.model.wr_data)
+ print_results("F2232HModel --> UserModel", model_rd_data, tb.user.rd_data)
+ print_results("UserModel --> FT2232HModel", user_wr_data, tb.model.wr_data)
if __name__ == "__main__":
main()
projects / litex.git / commitdiff