[sim] fixed FSR exception field bug

diff --git a/riscv/decode.h b/riscv/decode.h
index cf2ee575ed1c39da3527a74add3629edef4dd48a..499181dde373a0b756549d58301018b5b8c0e49d 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -63,7 +63,7 @@ const int JUMP_ALIGN_BITS = 1;
 #define FPEXC_NX 0x01
 #define FPEXC_UF 0x02
 #define FPEXC_OF 0x04
-#define FPEXC_DZ 0x02
+#define FPEXC_DZ 0x08
 #define FPEXC_NV 0x10
 
 #define FSR_AEXC_SHIFT 0