litesata: more pep8 (when convenient), should be almost OK

diff --git a/misoclib/mem/litesata/__init__.py b/misoclib/mem/litesata/__init__.py
index 3839db0fb85432b1fcbd59fb38cfa2cd308b5af2..21b64293ea1136fc3071b3a897e9b37868a3b529 100644 (file)
--- a/misoclib/mem/litesata/__init__.py
+++ b/misoclib/mem/litesata/__init__.py
@@ -19,4 +19,3 @@ class LiteSATA(Module, AutoCSR):
         self.submodules.crossbar = LiteSATACrossbar(self.core)
         if with_bist:
             self.submodules.bist = LiteSATABIST(self.crossbar, with_bist_csr)
-

diff --git a/misoclib/mem/litesata/core/command/__init__.py b/misoclib/mem/litesata/core/command/__init__.py
index 3af25fa45aa28e72d9438b22f386dabce21bc6d8..36a96913113a4e3d90f48155ed7a7440be0b665b 100644 (file)
--- a/misoclib/mem/litesata/core/command/__init__.py
+++ b/misoclib/mem/litesata/core/command/__init__.py
@@ -84,7 +84,8 @@ class LiteSATACommandTX(Module):
 
             transport.sink.stb.eq(sink.stb),
             transport.sink.sop.eq(dwords_counter.value == 0),
-            transport.sink.eop.eq((dwords_counter.value == (fis_max_dwords-1)) | sink.eop),
+            transport.sink.eop.eq((dwords_counter.value == (fis_max_dwords-1)) |
+                                  sink.eop),
 
             sink.ack.eq(transport.sink.ack),
             If(sink.stb & sink.ack,

diff --git a/misoclib/mem/litesata/core/link/__init__.py b/misoclib/mem/litesata/core/link/__init__.py
index e8a8ca5e56ccd95977467776d6c166ab9fbb083d..a6b80f3ae527e623e8d016843df0ef7132a14711 100644 (file)
--- a/misoclib/mem/litesata/core/link/__init__.py
+++ b/misoclib/mem/litesata/core/link/__init__.py
@@ -91,7 +91,9 @@ class LiteSATALinkTX(Module):
                 insert.eq(primitives["HOLDA"]),
             ).Elif(~scrambler.source.stb,
                 insert.eq(primitives["HOLD"]),
-            ).Elif(scrambler.source.stb & scrambler.source.eop & scrambler.source.ack,
+            ).Elif(scrambler.source.stb &
+                   scrambler.source.eop &
+                   scrambler.source.ack,
                 NextState("EOF")
             )
         )
@@ -247,7 +249,8 @@ class LiteSATALink(Module):
         self.submodules.tx_buffer = PacketBuffer(link_description(32), buffer_depth)
         self.submodules.tx = LiteSATALinkTX(phy)
         self.submodules.rx = LiteSATALinkRX(phy)
-        self.submodules.rx_buffer = PacketBuffer(link_description(32), buffer_depth, almost_full=3*buffer_depth//4)
+        self.submodules.rx_buffer = PacketBuffer(link_description(32), buffer_depth,
+                                                 almost_full=3*buffer_depth//4)
         self.comb += [
             Record.connect(self.tx_buffer.source, self.tx.sink),
             Record.connect(self.rx.to_tx, self.tx.from_rx),

diff --git a/misoclib/mem/litesata/core/link/crc.py b/misoclib/mem/litesata/core/link/crc.py
index 8600cf99bb2b3f2bb913af2604fe7071eafc0f00..7825a1743f15a61faa668c6281cc5baa5b476c91 100644 (file)
--- a/misoclib/mem/litesata/core/link/crc.py
+++ b/misoclib/mem/litesata/core/link/crc.py
@@ -88,6 +88,7 @@ class LiteSATACRC(Module):
     polynom = 0x04C11DB7
     init = 0x52325032
     check = 0x00000000
+
     def __init__(self, dw=32):
         self.d = Signal(self.width)
         self.value = Signal(self.width)

diff --git a/misoclib/mem/litesata/core/transport/__init__.py b/misoclib/mem/litesata/core/transport/__init__.py
index 4375f6c1ef8f502da31c776270024b690c9738f9..ed19b9b1770e974c1db04a4f377b185d41e28b04 100644 (file)
--- a/misoclib/mem/litesata/core/transport/__init__.py
+++ b/misoclib/mem/litesata/core/transport/__init__.py
@@ -104,7 +104,9 @@ class LiteSATATransportTX(Module):
 
         self.comb += [
             counter.ce.eq(sink.stb & link.sink.ack),
-            cmd_done.eq((counter.value == cmd_len) & link.sink.stb & link.sink.ack),
+            cmd_done.eq((counter.value == cmd_len) &
+                        link.sink.stb &
+                        link.sink.ack),
             If(cmd_send,
                 link.sink.stb.eq(sink.stb),
                 link.sink.sop.eq(counter.value == 0),

diff --git a/misoclib/mem/litesata/phy/ctrl.py b/misoclib/mem/litesata/phy/ctrl.py
index fa9080d36766c1435af88c71749d5c69ccb9627a..e73fb25857d83f77297e3a9cefcf385abe359ba8 100644 (file)
--- a/misoclib/mem/litesata/phy/ctrl.py
+++ b/misoclib/mem/litesata/phy/ctrl.py
@@ -140,7 +140,8 @@ class LiteSATAPHYCtrl(Module):
         ]
 
         self.comb +=  \
-            align_detect.eq(self.sink.stb & (self.sink.data == primitives["ALIGN"]))
+            align_detect.eq(self.sink.stb &
+                            (self.sink.data == primitives["ALIGN"]))
         self.sync += \
             If(fsm.ongoing("SEND_ALIGN"),
                 If(sink.stb,

diff --git a/misoclib/mem/litesata/phy/datapath.py b/misoclib/mem/litesata/phy/datapath.py
index aad7614bd5801ef98d1b43f176244292059dcf13..847a0d8bf1801b0cbd307eb477f106534d88e724 100644 (file)
--- a/misoclib/mem/litesata/phy/datapath.py
+++ b/misoclib/mem/litesata/phy/datapath.py
@@ -20,7 +20,9 @@ class LiteSATAPHYDatapathRX(Module):
                 last_charisk.eq(sink.charisk),
                 last_data.eq(sink.data)
             )
-        converter = Converter(phy_description(16), phy_description(32), reverse=False)
+        converter = Converter(phy_description(16),
+                              phy_description(32),
+                              reverse=False)
         converter = InsertReset(RenameClockDomains(converter, "sata_rx"))
         self.submodules += converter
         self.comb += [
@@ -71,7 +73,9 @@ class LiteSATAPHYDatapathTX(Module):
         self.comb += Record.connect(sink, fifo.sink)
 
     # width convertion (32 to 16)
-        converter = Converter(phy_description(32), phy_description(16), reverse=False)
+        converter = Converter(phy_description(32),
+                              phy_description(16),
+                              reverse=False)
         converter = RenameClockDomains(converter, "sata_tx")
         self.submodules += converter
         self.comb += [

diff --git a/misoclib/mem/litesata/test/crc_tb.py b/misoclib/mem/litesata/test/crc_tb.py
index feccf565a2f4f5713e7ec6906fcc912b50e07088..237a513f590b8aaadd9db24e21663e198c28a242 100644 (file)
--- a/misoclib/mem/litesata/test/crc_tb.py
+++ b/misoclib/mem/litesata/test/crc_tb.py
@@ -17,7 +17,9 @@ class TB(Module):
         for data in datas:
             stdin += "0x{:08x} ".format(data)
         stdin += "exit"
-        with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
+        with subprocess.Popen("./crc",
+                              stdin=subprocess.PIPE,
+                              stdout=subprocess.PIPE) as process:
             process.stdin.write(stdin.encode("ASCII"))
             out, err = process.communicate()
         return int(out.decode("ASCII"), 16)

diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py
index 06cb9a2a437cd92eabd533804ee650d51ea54d5f..a9f66bfabdb4002e2d85321dbf3b1793855e4da0 100644 (file)
--- a/misoclib/mem/litesata/test/hdd.py
+++ b/misoclib/mem/litesata/test/hdd.py
@@ -96,7 +96,9 @@ def print_link(s):
 
 
 def import_scrambler_datas():
-    with subprocess.Popen(["./scrambler"], stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
+    with subprocess.Popen(["./scrambler"],
+                          stdin=subprocess.PIPE,
+                          stdout=subprocess.PIPE) as process:
         process.stdin.write("0x10000".encode("ASCII"))
         out, err = process.communicate()
     return [int(e, 16) for e in out.decode("utf-8").split("\n")[:-1]]
@@ -121,7 +123,9 @@ class LinkRXPacket(LinkPacket):
         for v in self[:-1]:
             stdin += "0x{:08x} ".format(v)
         stdin += "exit"
-        with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
+        with subprocess.Popen("./crc",
+                              stdin=subprocess.PIPE,
+                              stdout=subprocess.PIPE) as process:
             process.stdin.write(stdin.encode("ASCII"))
             out, err = process.communicate()
         crc = int(out.decode("ASCII"), 16)
@@ -140,7 +144,9 @@ class LinkTXPacket(LinkPacket):
         for v in self:
             stdin += "0x{:08x} ".foramt(v)
         stdin += "exit"
-        with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
+        with subprocess.Popen("./crc",
+                              stdin=subprocess.PIPE,
+                              stdout=subprocess.PIPE) as process:
             process.stdin.write(stdin.encode("ASCII"))
             out, err = process.communicate()
         crc = int(out.decode("ASCII"), 16)

diff --git a/misoclib/mem/litesata/test/scrambler_tb.py b/misoclib/mem/litesata/test/scrambler_tb.py
index 049ba353587729b187280d3111a87a259b5437a8..3d36831fdf6d143969ae0f8f71e1a140bb31edba 100644 (file)
--- a/misoclib/mem/litesata/test/scrambler_tb.py
+++ b/misoclib/mem/litesata/test/scrambler_tb.py
@@ -13,7 +13,9 @@ class TB(Module):
 
     def get_c_values(self, length):
         stdin = "0x{:08x}".format(length)
-        with subprocess.Popen("./scrambler", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
+        with subprocess.Popen("./scrambler",
+                              stdin=subprocess.PIPE,
+                              stdout=subprocess.PIPE) as process:
             process.stdin.write(stdin.encode("ASCII"))
             out, err = process.communicate()
         return [int(e, 16) for e in out.decode("ASCII").split("\n")[:-1]]