build.plat: add iter_extra_files method.

* vendor.*: employ iter_extra_files.

diff --git a/nmigen/build/plat.py b/nmigen/build/plat.py
index 7de062a8507711d2dcd2b3e7794123fceb03c857..3de59f5bd8688f6fe664116db0672cf164f8be78 100644 (file)
--- a/nmigen/build/plat.py
+++ b/nmigen/build/plat.py
@@ -281,3 +281,6 @@ class TemplatedPlatform(Platform):
         for filename, content in self.extra_files.items():
             plan.add_file(filename, content)
         return plan
+
+    def iter_extra_files(self, *endswith):
+        return (f for f in self.extra_files if f.endswith(endswith))

diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py
index d34dbca53a580159e420b15f040a06d590b505b8..62a6ed57b154039c0b8228a63d85069a1ed57934 100644 (file)
--- a/nmigen/vendor/lattice_ecp5.py
+++ b/nmigen/vendor/lattice_ecp5.py
@@ -67,12 +67,11 @@ class LatticeECP5Platform(TemplatedPlatform):
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
-            {% for file in platform.extra_files %}
-                {% if file.endswith(".v") -%}
-                    read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
-                {% elif file.endswith(".sv") -%}
-                    read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
-                {% endif %}
+            {% for file in platform.iter_extra_files(".v") -%}
+                read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
+            {% endfor %}
+            {% for file in platform.iter_extra_files(".sv") -%}
+                read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
             {% endfor %}
             read_ilang {{name}}.il
             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}

diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py
index 02c9459e25bcb83211251e958c9666ece9cce599..73db3aa14af790f46958b32d277a3afa72b4bfa7 100644 (file)
--- a/nmigen/vendor/lattice_ice40.py
+++ b/nmigen/vendor/lattice_ice40.py
@@ -59,12 +59,11 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
-            {% for file in platform.extra_files %}
-                {% if file.endswith(".v") -%}
-                    read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
-                {% elif file.endswith(".sv") -%}
-                    read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
-                {% endif %}
+            {% for file in platform.iter_extra_files(".v") -%}
+                read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
+            {% endfor %}
+            {% for file in platform.iter_extra_files(".sv") -%}
+                read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
             {% endfor %}
             read_ilang {{name}}.il
             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index b0f8f99b0610cf932113380eded1f304339c0456..a24f664f86e36fe4e7964f966de69cda5bffc688 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -55,17 +55,13 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         "{{name}}.tcl": r"""
             # {{autogenerated}}
             create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
-            {% for file in platform.extra_files %}
-                {% if file.endswith((".v", ".sv")) -%}
-                    add_files {{file}}
-                {% endif %}
+            {% for file in platform.iter_extra_files(".v", ".sv") -%}
+                add_files {{file}}
             {% endfor %}
             add_files {{name}}.v
             read_xdc {{name}}.xdc
-            {% for file in platform.extra_files %}
-                {% if file.endswith("xdc") -%}
-                    read_xdc {{file}}
-                {% endif %}
+            {% for file in platform.iter_extra_files(".xdc") -%}
+                read_xdc {{file}}
             {% endfor %}
             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
             synth_design -top {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}

diff --git a/nmigen/vendor/xilinx_spartan6.py b/nmigen/vendor/xilinx_spartan6.py
index fef946189d233fb9052f9431df707a626d8ef24d..5128bf9c896b602d36a91876fe45395e42ffebde 100644 (file)
--- a/nmigen/vendor/xilinx_spartan6.py
+++ b/nmigen/vendor/xilinx_spartan6.py
@@ -57,10 +57,8 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         """,
         "{{name}}.prj": r"""
             # {{autogenerated}}
-            {% for file in platform.extra_files -%}
-                {% if file.endswith(".v") %}
-                    verilog work {{file}}
-                {% endif %}
+            {% for file in platform.iter_extra_files(".v") -%}
+                verilog work {{file}}
             {% endfor %}
             verilog work {{name}}.v
         """,