re PR target/84844 (ICE in extract_constrain_insn_cached, at recog.c:2217 (error...

	PR target/84844
	Revert
	2017-04-20  Uros Bizjak  <ubizjak@gmail.com>

	PR target/78090
	* config/i386/constraints.md (Yc): New register constraint.
	* config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed):
	Use Yc constraint for alternative 2 of operand 0.  Remove
	preferred_for_speed attribute.

	* gcc.target/i386/pr84844.c: New test.

From-SVN: r258515

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 550e2b6b3e003b9a96109f4c99b7f74d71b0111b..3e174c58cbf21e296ec4719477411f2a3edbe19d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2018-03-14  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/84844
+       Revert
+       2017-04-20  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/78090
+       * config/i386/constraints.md (Yc): New register constraint.
+       * config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed):
+       Use Yc constraint for alternative 2 of operand 0.  Remove
+       preferred_for_speed attribute.
+
 2018-03-14  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/84830

diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index d026968c4c906cd42602480d542760bd1bf9db1b..f9564d3a385c5f3553e7c870686e68ec96bdc8ef 100644 (file)
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -99,7 +99,6 @@
 
 ;; We use the Y prefix to denote any number of conditional register sets:
 ;;  z  First SSE register.
-;;  c  SSE inter-unit conversions enabled
 ;;  i  SSE2 inter-unit moves to SSE register enabled
 ;;  j  SSE2 inter-unit moves from SSE register enabled
 ;;  d  any EVEX encodable SSE register for AVX512BW target or any SSE register
@@ -124,10 +123,6 @@
 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
  "First SSE register (@code{%xmm0}).")
 
-(define_register_constraint "Yc"
- "TARGET_SSE && TARGET_INTER_UNIT_CONVERSIONS ? ALL_SSE_REGS : NO_REGS"
- "@internal Any SSE register, when SSE and inter-unit conversions are enabled.")
-
 (define_register_constraint "Yi"
  "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
  "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.")

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index bd44243cd2f0f1bd1c104e28eee22f855f33bf4e..2b73e8f61871bd3e35d8385463a2d3c493ecda11 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5325,7 +5325,7 @@
 })
 
 (define_insn "*float<SWI48:mode><MODEF:mode>2_mixed"
-  [(set (match_operand:MODEF 0 "register_operand" "=f,Yc,v")
+  [(set (match_operand:MODEF 0 "register_operand" "=f,v,v")
        (float:MODEF
          (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
   "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
@@ -5354,6 +5354,10 @@
                            && X87_ENABLE_FLOAT (<MODEF:MODE>mode,
                                                 <SWI48:MODE>mode)")
            ]
+           (symbol_ref "true")))
+   (set (attr "preferred_for_speed")
+     (cond [(eq_attr "alternative" "1")
+              (symbol_ref "TARGET_INTER_UNIT_CONVERSIONS")]
            (symbol_ref "true")))])
 
 (define_insn "*float<SWI48x:mode><MODEF:mode>2_i387"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0175d4342c0a56ae285cd2b2000575400d5e9a9f..215e30220541b6ab76c17b65eaf080f7bd5934ec 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-03-14  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/84844
+       * gcc.target/i386/pr84844.c: New test.
+
 2018-03-14  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/84830

diff --git a/gcc/testsuite/gcc.target/i386/pr84844.c b/gcc/testsuite/gcc.target/i386/pr84844.c
new file mode 100644 (file)
index 0000000..16e1416
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr84844.c
@@ -0,0 +1,10 @@
+/* PR target/84844 */
+/* { dg-do compile } */
+/* { dg-options "-march=bdver1 -O2 -fschedule-insns -fselective-scheduling" } */
+
+double
+foo (int *x, int y, int z)
+{
+  *x = y;
+  return z;
+}