Add SPI configuration to Xilinx constraint files

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc
index 481d8e4c67338063d39721ef70b4db0573cc178e..a635211a8b46689eff8d7c4095afa87bdb232073 100644 (file)
--- a/fpga/arty_a7.xdc
+++ b/fpga/arty_a7.xdc
@@ -8,3 +8,7 @@ set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart0_
 
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property CFGBVS VCCO [current_design]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]

diff --git a/fpga/cmod_a7-35.xdc b/fpga/cmod_a7-35.xdc
index 5f4aab26423ac3bf515b2fb530d2cd44f5452669..3492d54c425ab3ca008922a7155bf2e3941cc65a 100644 (file)
--- a/fpga/cmod_a7-35.xdc
+++ b/fpga/cmod_a7-35.xdc
@@ -6,3 +6,10 @@ set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { uart0_
 set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd  }];
 
 set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]

diff --git a/fpga/nexys-video.xdc b/fpga/nexys-video.xdc
index 6fc09f392c7e51d3ab32e893f64103e4d985ba16..239376f5497897852673856ed9de3cc1442e7808 100644 (file)
--- a/fpga/nexys-video.xdc
+++ b/fpga/nexys-video.xdc
@@ -8,3 +8,7 @@ set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart0_rxd]
 
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property CFGBVS VCCO [current_design]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]

diff --git a/fpga/nexys_a7.xdc b/fpga/nexys_a7.xdc
index 08e73e277f348b02aa37bf0d94a11a521e260625..a572772e6e144dbf7fa464ab5601ebd3bb95cd5e 100644 (file)
--- a/fpga/nexys_a7.xdc
+++ b/fpga/nexys_a7.xdc
@@ -8,3 +8,7 @@ set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports uart0_rxd]
 
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property CFGBVS VCCO [current_design]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]