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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 4b843a0f50373e4cad25ab622dce6880871bebbb..54dc1489c4cda6e9d0314e19456a0823df100ce5 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -23,8 +23,11 @@ has allowed significant apparent speed increases: 3200 mhz DDR4 and
 even faster DDR5, and other advanced Memory interfaces such as HBM,
 Gen-Z, and OpenCAPI, all make an effort, but these efforts are
 dwarfed by the two nearly three orders of magnitude increase in
-CPU horsepower.  Some systems at the time of writing are approaching
-a *Gigabyte* of L4 Cache, by way of compensation.
+CPU horsepower. Seymour Cray, from his amazing in-depth knowledge,
+predicted that the mismatch would become a serious limitation.
+Some systems at the time of writing are approaching
+a *Gigabyte* of L4 Cache, by way of compensation, and as we know
+from experience even that will be considered inadequate in future.
 
 Efforts to solve this problem by moving the processing closer to
 or directly integrated into the memory have traditionally not gone
@@ -36,6 +39,8 @@ same "specialist parallel processing" mistake, betting heavily on
 AI with Matrix and Convolution Engines that can do no other task.
 Aspex only survived by being bought by Ericsson, where its specialised
 suitability for massive wide Baseband FFTs saved it from going under.
+Any "better AI mousetrap" that comes along will quickly render
+both D-Matrix and Graphcore obsolete.
 
 Second hints as to the answer emerge from an article
 "[SIMD considered harmful](https://www.sigarch.org/simd-instructions-considered-harmful/)"