Move xor of input into insn doing int->double conversion.

From-SVN: r12324

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0dc5f4cb572997995a20dd34003026de6edb1ca3..2c3f4eddd446176a9e72703768743462dc0170ca 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3549,16 +3549,14 @@
                   (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
              (use (match_dup 2))
              (use (match_dup 3))
+             (clobber (match_dup 4))
              (clobber (reg:DF 76))])]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   "
 {
-  rtx low = gen_reg_rtx (SImode);
   operands[2] = force_reg (SImode, GEN_INT (0x43300000));
   operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
-
-  emit_insn (gen_xorsi3 (low, operands[1], GEN_INT (0x80000000)));
-  operands[1] = low;
+  operands[4] = gen_reg_rtx (SImode);
 }")
 
 (define_insn "*floatsidf2_internal"
@@ -3566,32 +3564,41 @@
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
    (use (match_operand:SI 2 "gpc_reg_operand" "r"))
    (use (match_operand:DF 3 "gpc_reg_operand" "f"))
+   (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
    (clobber (reg:DF 76))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   "#"
-  [(set_attr "length" "16")])
+  [(set_attr "length" "20")])
 
 (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
    (use (match_operand:SI 2 "gpc_reg_operand" ""))
    (use (match_operand:DF 3 "gpc_reg_operand" ""))
+   (clobber (match_operand:SI 4 "gpc_reg_operand" ""))
    (clobber (reg:DF 76))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   [(set (match_dup 4)
-       (unspec [(match_dup 1)          ;; low word
+       (xor:SI (match_dup 1)
+               (match_dup 5)))
+   (set (match_dup 6)
+       (unspec [(match_dup 4)          ;; low word
                 (reg:SI 1)] 11))
-   (set (match_dup 4)
+   (set (match_dup 6)
        (unspec [(match_dup 2)          ;; high word
                 (reg:SI 1)
-                (match_dup 4)] 12))
+                (match_dup 6)] 12))
    (set (match_dup 0)
-       (unspec [(match_dup 4)
+       (unspec [(match_dup 6)
                 (reg:SI 1)] 13))
    (set (match_dup 0)
        (minus:DF (match_dup 0)
                  (match_dup 3)))]
-  "operands[4] = gen_rtx (REG, DFmode, FPMEM_REGNUM);")
+  "
+{
+  operands[5] = GEN_INT (0x80000000);
+  operands[6] = gen_rtx (REG, DFmode, FPMEM_REGNUM);
+}")
 
 (define_expand "floatunssidf2"
   [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")