arch-x86: Change insertBits in TLB translateFunctional

x86 TLB::translateFunctional inserts one too many bits from the virtual
address leading to an incorrect physical address occasionally.

Change-Id: I2cc551c496f7ce729ea440ef01a680c0de257269
JIRA: https://gem5.atlassian.net/browse/GEM5-442
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27827
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index baeeb66bdbb8639cb611ffa97139e08cf0fad626..ceccba892f4beb663942996752d82c6ae7a2e0a8 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -473,7 +473,7 @@ TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
         Fault fault = walker->startFunctional(tc, addr, logBytes, mode);
         if (fault != NoFault)
             return fault;
-        paddr = insertBits(addr, logBytes, 0, vaddr);
+        paddr = insertBits(addr, logBytes - 1, 0, vaddr);
     } else {
         Process *process = tc->getProcessPtr();
         const auto *pte = process->pTable->lookup(vaddr);