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Remove check for cell->name[0] == '$'
author
Eddie Hung
<eddieh@ece.ubc.ca>
Wed, 6 Feb 2019 22:53:40 +0000
(14:53 -0800)
committer
Eddie Hung
<eddieh@ece.ubc.ca>
Wed, 6 Feb 2019 22:53:40 +0000
(14:53 -0800)
backends/verilog/verilog_backend.cc
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diff --git
a/backends/verilog/verilog_backend.cc
b/backends/verilog/verilog_backend.cc
index 66a9e70d3785e6a5e75ecd72ce94d19f78e73b31..7b3a60e61e9f5693aa64d4e35d499ed1746d3f4a 100644
(file)
--- a/
backends/verilog/verilog_backend.cc
+++ b/
backends/verilog/verilog_backend.cc
@@
-1248,7
+1248,7
@@
void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
std::string init;
- if (
cell->name[0] == '$' &&
reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+ if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
std::stringstream ss;
dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
init = ss.str();