(no commit message)

diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn
index 1939a6a98a1cafd3e49ef8952ff32f237c2ddc8d..292f45af2d3bf1ecbea5b08de4944b65bad30ea6 100644 (file)
--- a/nlnet_2023_svp64_riscv.mdwn
+++ b/nlnet_2023_svp64_riscv.mdwn
@@ -65,8 +65,9 @@ EUR 100,000.
   Many of these were already written four years ago and need conversion
   to the new format used in Libre-SOC
   <https://git.libre-soc.org/?p=riscv-tests.git;a=shortlog;h=refs/heads/sv>
-* Documentation, demonstrations and Conference Papers. This is a big
-  project and is important to engage in outreach. 
+* Documentation, demonstrations and Conference Papers. Also many
+  of the other projects (cryptoprimitives, video) will need porting
+  of the Power ISA SVP64 Assembler to SimpleV-RISCV.
 * Research and assessment of ARM7 and i486 (both on opencores.org)
   as to their feasibility for applying Simple-V Prefixing