/* If a swizzle was provided, we need to swizzle the clear color so that
* the hardware color format conversion will work properly.
*/
- params.dst.clear_color = swizzle_color_value(params.dst.clear_color,
- swizzle);
+ params.dst.clear_color =
+ isl_color_value_swizzle_inv(params.dst.clear_color, swizzle);
batch->blorp->exec(batch, ¶ms);
}
-union isl_color_value
-swizzle_color_value(union isl_color_value src, struct isl_swizzle swizzle)
-{
- union isl_color_value dst = { .u32 = { 0, } };
-
- /* We assign colors in ABGR order so that the first one will be taken in
- * RGBA precedence order. According to the PRM docs for shader channel
- * select, this matches Haswell hardware behavior.
- */
- if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
- dst.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = src.u32[3];
- if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
- dst.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = src.u32[2];
- if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
- dst.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = src.u32[1];
- if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
- dst.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = src.u32[0];
-
- return dst;
-}
-
void
blorp_clear(struct blorp_batch *batch,
const struct blorp_surf *surf,
* also ensures that they work on pre-Haswell hardware which can't swizlle
* at all.
*/
- clear_color = swizzle_color_value(clear_color, swizzle);
+ clear_color = isl_color_value_swizzle_inv(clear_color, swizzle);
swizzle = ISL_SWIZZLE_IDENTITY;
bool clear_rgb_as_red = false;
* around it by swapping the colors around and using B4G4R4A4 instead.
*/
const struct isl_swizzle ARGB = ISL_SWIZZLE(ALPHA, RED, GREEN, BLUE);
- clear_color = swizzle_color_value(clear_color, ARGB);
+ clear_color = isl_color_value_swizzle_inv(clear_color, ARGB);
format = ISL_FORMAT_B4G4R4A4_UNORM;
} else if (isl_format_get_layout(format)->bpb % 3 == 0) {
clear_rgb_as_red = true;
return (struct isl_swizzle) { chans[0], chans[1], chans[2], chans[3] };
}
+/** Applies an inverse swizzle to a color value */
+union isl_color_value
+isl_color_value_swizzle_inv(union isl_color_value src,
+ struct isl_swizzle swizzle)
+{
+ union isl_color_value dst = { .u32 = { 0, } };
+
+ /* We assign colors in ABGR order so that the first one will be taken in
+ * RGBA precedence order. According to the PRM docs for shader channel
+ * select, this matches Haswell hardware behavior.
+ */
+ if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
+ dst.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = src.u32[3];
+ if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
+ dst.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = src.u32[2];
+ if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
+ dst.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = src.u32[1];
+ if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
+ dst.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = src.u32[0];
+
+ return dst;
+}
+
uint8_t
isl_format_get_aux_map_encoding(enum isl_format format)
{