spu-protos.c (spu_split_address): Add.

	* config/spu/spu-protos.c (spu_split_address): Add.
	* config/spu/spu.c (spu_split_address): Add.
	(print_operand): Handle HIGH.
	(spu_legitimate_address):  Don't test for aligned CONST.
	(spu_expand_mov):  Don't split addresses here.
	* config/spu/constraints.md (A): Don't test legitimate_const.
	* config/spu/spu.md: Add split of movsi patterns for PIC mode.
	(ceq_di): Use correct predicates.

From-SVN: r119532

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9ae153bbddebbac77d466fa826260e60e1cb648b..d2a87437d79603226d2d34d8f8908c930b5297ee 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2006-12-04  Trevor Smigiel  <trevor_smigiel@playstation.sony.com>
+
+       * config/spu/spu-protos.c (spu_split_address): Add.
+       * config/spu/spu.c (spu_split_address): Add.
+       (print_operand): Handle HIGH.
+       (spu_legitimate_address):  Don't test for aligned CONST.
+       (spu_expand_mov):  Don't split addresses here.
+       * config/spu/constraints.md (A): Don't test legitimate_const.
+       * config/spu/spu.md: Add split of movsi patterns for PIC mode.
+       (ceq_di): Use correct predicates.
+
 2006-12-04  Eric Christopher  <echristo@apple.com>
 
        * config/darwin.h: Update copyright notice.

diff --git a/gcc/config/spu/constraints.md b/gcc/config/spu/constraints.md
index 6c4fb0819230fdee6a5547abee003c59007c1860..4fa96ce224c4cb8ee8e963c139b57c089d7f6a3f 100644 (file)
--- a/gcc/config/spu/constraints.md
+++ b/gcc/config/spu/constraints.md
@@ -28,10 +28,7 @@
   "An immediate which can be loaded with the il/ila/ilh/ilhu instructions.  const_int is treated as a 32 bit value."
   (ior (and (match_code "const_int,const_double,const_vector")
            (match_test "immediate_load_p (op, SImode)"))
-       (and (match_test "!TARGET_LARGE_MEM && !flag_pic")
-           (ior (match_code "symbol_ref,label_ref")
-                (and (match_code "const")
-                     (match_test "legitimate_const (op, 0)"))))))
+       (match_code "symbol_ref,label_ref,high,const")))
 
 (define_constraint "B"
   "An immediate for arithmetic instructions (e.g., ai, ceqi).  const_int is treated as a 32 bit value."

diff --git a/gcc/config/spu/spu-protos.h b/gcc/config/spu/spu-protos.h
index a42210dbc3ca69cc49ffa1348b3d792cd183d758..3239745ee0e8cfe300657827238e2e804e63ffb7 100644 (file)
--- a/gcc/config/spu/spu-protos.h
+++ b/gcc/config/spu/spu-protos.h
@@ -34,6 +34,7 @@ extern HOST_WIDE_INT const_double_to_hwint (rtx x);
 extern rtx hwint_to_const_double (enum machine_mode mode, HOST_WIDE_INT v);
 extern void print_operand_address (FILE * file, register rtx addr);
 extern void print_operand (FILE * file, rtx x, int code);
+extern void spu_split_address (rtx * ops);
 extern int spu_saved_regs_size (void);
 extern int direct_return (void);
 extern void spu_expand_prologue (void);

diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index 055c414c70528b0e07979701041b33ae5d98f857..d6c420a444d81cdfdcbcf0404e11110cc952e5f4 100644 (file)
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -1088,6 +1088,8 @@ print_operand (FILE * file, rtx x, int code)
        }
       else if (xcode == SYMBOL_REF || xcode == LABEL_REF || xcode == CONST)
        fprintf (file, "a");
+      else if (xcode == HIGH)
+       fprintf (file, "hu");
       else
        gcc_unreachable ();
       return;
@@ -1118,6 +1120,11 @@ print_operand (FILE * file, rtx x, int code)
        }
       else if (xcode == CONST || xcode == SYMBOL_REF || xcode == LABEL_REF)
        output_addr_const (file, x);
+      else if (xcode == HIGH)
+       {
+         output_addr_const (file, XEXP (x, 0));
+         fprintf (file, "@h");
+       }
       else
        gcc_unreachable ();
       return;
@@ -1267,6 +1274,27 @@ get_pic_reg (void)
   return pic_reg;
 }
 
+/* Split constant addresses to handle cases that are too large.  Also, add in
+   the pic register when in PIC mode. */
+void
+spu_split_address (rtx * ops)
+{
+  if (TARGET_LARGE_MEM
+      || (GET_CODE (ops[1]) == CONST && !legitimate_const (ops[1], 0)))
+    {
+      emit_insn (gen_high (ops[0], ops[1]));
+      emit_insn (gen_low (ops[0], ops[0], ops[1]));
+    }
+  else if (flag_pic)
+    emit_insn (gen_pic (ops[0], ops[1]));
+  if (flag_pic)
+    {
+      rtx pic_reg = get_pic_reg ();
+      emit_insn (gen_addsi3 (ops[0], ops[0], pic_reg));
+      current_function_uses_pic_offset_table = 1;
+    }
+}
+
 /* SAVING is TRUE when we are generating the actual load and store
    instructions for REGNO.  When determining the size of the stack
    needed for saving register we must allocate enough space for the
@@ -2408,7 +2436,7 @@ spu_legitimate_address (enum machine_mode mode ATTRIBUTE_UNUSED,
       return !TARGET_LARGE_MEM;
 
     case CONST:
-      return !TARGET_LARGE_MEM && legitimate_const (x, 1);
+      return !TARGET_LARGE_MEM && legitimate_const (x, 0);
 
     case CONST_INT:
       return INTVAL (x) >= 0 && INTVAL (x) <= 0x3ffff;
@@ -3091,34 +3119,6 @@ spu_expand_mov (rtx * ops, enum machine_mode mode)
          emit_insn (gen_rtx_SET (VOIDmode, to, gen_rtx_IOR (mode, to, lo)));
          return 1;
        }
-      if ((GET_CODE (ops[1]) == CONST
-           && !legitimate_const (ops[1], 0))
-         || (TARGET_LARGE_MEM
-             && (GET_CODE (ops[1]) == CONST
-                 || GET_CODE (ops[1]) == SYMBOL_REF
-                 || GET_CODE (ops[1]) == LABEL_REF)))
-       {
-         emit_insn (gen_high (ops[0], ops[1]));
-         emit_insn (gen_low (ops[0], ops[0], ops[1]));
-         if (flag_pic)
-           {
-             rtx pic_reg = get_pic_reg ();
-             emit_insn (gen_addsi3 (ops[0], ops[0], pic_reg));
-             current_function_uses_pic_offset_table = 1;
-           }
-         return 1;
-       }
-      if (flag_pic
-         && (GET_CODE (ops[1]) == SYMBOL_REF
-             || GET_CODE (ops[1]) == LABEL_REF
-             || GET_CODE (ops[1]) == CONST))
-       {
-         rtx pic_reg = get_pic_reg ();
-         emit_insn (gen_pic (ops[0], ops[1]));
-         emit_insn (gen_addsi3 (ops[0], ops[0], pic_reg));
-         current_function_uses_pic_offset_table = 1;
-         return 1;
-       }
       return 0;
     }
   else

diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index 70cf1995cfffe53eb150d673c4288c9bee7a093a..4f048801ecfcf126ebcc613ef93655176eda657f 100644 (file)
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -237,6 +237,29 @@
       DONE;
   })
 
+(define_split 
+  [(set (match_operand:SI 0 "spu_reg_operand" "=r")
+       (match_operand:SI 1 "immediate_operand" "s"))]
+
+  "(flag_pic || TARGET_LARGE_MEM
+    || (GET_CODE (operands[1]) == CONST
+        && !legitimate_const (operands[1], 0)))
+   && (reload_in_progress || reload_completed)
+   && (GET_CODE (operands[1]) == CONST
+       || GET_CODE (operands[1]) == SYMBOL_REF
+       || GET_CODE (operands[1]) == LABEL_REF)"
+  [(parallel
+    [(set (match_dup:SI 0)
+         (match_dup:SI 1))
+     (use (const_int 0))])
+   (set (match_dup:SI 0)
+       (plus:SI (match_dup:SI 0)
+                (match_dup:SI 2)))]
+  {
+    spu_split_address(operands);
+    DONE;
+  })
+
 (define_insn "pic"
   [(set (match_operand:SI 0 "spu_reg_operand" "=r")
        (match_operand:SI 1 "immediate_operand" "s"))
@@ -2408,9 +2431,9 @@
   ceq<bh>i\t%0,%1,%2")
 
 (define_insn_and_split "ceq_di"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (eq:SI (match_operand:DI 1 "register_operand" "r")
-              (match_operand:DI 2 "register_operand" "r")))]
+  [(set (match_operand:SI 0 "spu_reg_operand" "=r")
+        (eq:SI (match_operand:DI 1 "spu_reg_operand" "r")
+              (match_operand:DI 2 "spu_reg_operand" "r")))]
   ""
   "#"
   "reload_completed"