freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>

diff --git a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
index 3811bc530c2f54ea277bcfc08a386945b5d531d6..a315f5c5d903d630fa5421803973a70c2a7e5722 100644 (file)
--- a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
+++ b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14748 bytes, from 2015-04-12 15:01:13)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  57486 bytes, from 2015-04-12 18:10:00)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)

diff --git a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
index 8d15ed48e14734e5ba493faaaf9c61b07d4e6a50..0cccff1878b8dba149478a6da793345d343165df 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
+++ b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14748 bytes, from 2015-04-12 15:01:13)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  57486 bytes, from 2015-04-12 18:10:00)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -216,14 +216,24 @@ enum a3xx_color_fmt {
        RB_R10G10B10A2_UNORM = 16,
        RB_A8_UNORM = 20,
        RB_R8_UNORM = 21,
+       RB_R16_FLOAT = 24,
+       RB_R16G16_FLOAT = 25,
        RB_R16G16B16A16_FLOAT = 27,
        RB_R11G11B10_FLOAT = 28,
+       RB_R16_SNORM = 32,
+       RB_R16G16_SNORM = 33,
+       RB_R16G16B16A16_SNORM = 35,
+       RB_R16_UNORM = 36,
+       RB_R16G16_UNORM = 37,
+       RB_R16G16B16A16_UNORM = 39,
        RB_R16_SINT = 40,
        RB_R16G16_SINT = 41,
        RB_R16G16B16A16_SINT = 43,
        RB_R16_UINT = 44,
        RB_R16G16_UINT = 45,
        RB_R16G16B16A16_UINT = 47,
+       RB_R32_FLOAT = 48,
+       RB_R32G32_FLOAT = 49,
        RB_R32G32B32A32_FLOAT = 51,
        RB_R32_SINT = 52,
        RB_R32G32_SINT = 53,
@@ -272,6 +282,12 @@ enum a3xx_intp_mode {
        FLAT = 1,
 };
 
+enum a3xx_repl_mode {
+       S = 1,
+       T = 2,
+       ONE_T = 3,
+};
+
 enum a3xx_tex_filter {
        A3XX_TEX_NEAREST = 0,
        A3XX_TEX_LINEAR = 1,
@@ -758,7 +774,7 @@ static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT                 0
 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
 {
-       return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
+       return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
 }
 
 #define REG_A3XX_GRAS_SU_MODE_CONTROL                          0x00002070
@@ -1259,9 +1275,21 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v
 
 #define REG_A3XX_RB_STENCIL_CLEAR                              0x00002105
 
-#define REG_A3XX_RB_STENCIL_BUF_INFO                           0x00002106
+#define REG_A3XX_RB_STENCIL_INFO                               0x00002106
+#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK                        0xfffff800
+#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT               11
+static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
+{
+       return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
+}
 
-#define REG_A3XX_RB_STENCIL_BUF_PITCH                          0x00002107
+#define REG_A3XX_RB_STENCIL_PITCH                              0x00002107
+#define A3XX_RB_STENCIL_PITCH__MASK                            0xffffffff
+#define A3XX_RB_STENCIL_PITCH__SHIFT                           0
+static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
+{
+       return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
+}
 
 #define REG_A3XX_RB_STENCILREFMASK                             0x00002108
 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK                        0x000000ff
@@ -1369,6 +1397,7 @@ static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_
 {
        return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
 }
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE                  0x00001000
 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART                        0x00100000
 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST               0x02000000
 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE                            0x04000000
@@ -1818,6 +1847,102 @@ static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
 
 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK                 0x00000003
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT                        0
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK                 0x0000000c
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT                        2
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK                 0x00000030
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT                        4
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK                 0x000000c0
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT                        6
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK                 0x00000300
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT                        8
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK                 0x00000c00
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT                        10
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK                 0x00003000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT                        12
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK                 0x0000c000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT                        14
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK                 0x00030000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT                        16
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK                 0x000c0000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT                        18
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK                 0x00300000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT                        20
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK                 0x00c00000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT                        22
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK                 0x03000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT                        24
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK                 0x0c000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT                        26
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK                 0x30000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT                        28
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK;
+}
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK                 0xc0000000
+#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT                        30
+static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val)
+{
+       return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK;
+}
 
 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0                     0x0000228a
 
@@ -2680,7 +2805,7 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
 }
 
 #define REG_A3XX_TEX_CONST_3                                   0x00000003
-#define A3XX_TEX_CONST_3_LAYERSZ1__MASK                                0x00001fff
+#define A3XX_TEX_CONST_3_LAYERSZ1__MASK                                0x00007fff
 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT                       0
 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
 {

diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
index 0e80564d999c40f019a36e1f586d8fb048a61e08..0f69205e0548cbd6e65ecca75b0a25f0ae10afb1 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
+++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14748 bytes, from 2015-04-12 15:01:13)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  57486 bytes, from 2015-04-12 18:10:00)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -43,10 +43,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 enum a4xx_color_fmt {
        RB4_A8_UNORM = 1,
+       RB4_R8_UNORM = 2,
+       RB4_R4G4B4A4_UNORM = 8,
+       RB4_R5G5B5A1_UNORM = 10,
        RB4_R5G6R5_UNORM = 14,
-       RB4_Z16_UNORM = 15,
+       RB4_R8G8_UNORM = 15,
+       RB4_R8G8_SNORM = 16,
+       RB4_R8G8_UINT = 17,
+       RB4_R8G8_SINT = 18,
+       RB4_R16_FLOAT = 21,
+       RB4_R16_UINT = 22,
+       RB4_R16_SINT = 23,
        RB4_R8G8B8_UNORM = 25,
        RB4_R8G8B8A8_UNORM = 26,
+       RB4_R8G8B8A8_SNORM = 28,
+       RB4_R8G8B8A8_UINT = 29,
+       RB4_R8G8B8A8_SINT = 30,
+       RB4_R10G10B10A2_UNORM = 31,
+       RB4_R10G10B10A2_UINT = 34,
+       RB4_R11G11B10_FLOAT = 39,
+       RB4_R16G16_FLOAT = 42,
+       RB4_R16G16_UINT = 43,
+       RB4_R16G16_SINT = 44,
+       RB4_R32_FLOAT = 45,
+       RB4_R32_UINT = 46,
+       RB4_R32_SINT = 47,
+       RB4_R16G16B16A16_FLOAT = 54,
+       RB4_R16G16B16A16_UINT = 55,
+       RB4_R16G16B16A16_SINT = 56,
+       RB4_R32G32_FLOAT = 57,
+       RB4_R32G32_UINT = 58,
+       RB4_R32G32_SINT = 59,
+       RB4_R32G32B32A32_FLOAT = 60,
+       RB4_R32G32B32A32_UINT = 61,
+       RB4_R32G32B32A32_SINT = 62,
 };
 
 enum a4xx_tile_mode {
@@ -91,7 +121,14 @@ enum a4xx_vtx_fmt {
        VFMT4_16_16_UNORM = 29,
        VFMT4_16_16_16_UNORM = 30,
        VFMT4_16_16_16_16_UNORM = 31,
+       VFMT4_32_UINT = 32,
+       VFMT4_32_32_UINT = 33,
+       VFMT4_32_32_32_UINT = 34,
+       VFMT4_32_32_32_32_UINT = 35,
+       VFMT4_32_SINT = 36,
        VFMT4_32_32_SINT = 37,
+       VFMT4_32_32_32_SINT = 38,
+       VFMT4_32_32_32_32_SINT = 39,
        VFMT4_8_UINT = 40,
        VFMT4_8_8_UINT = 41,
        VFMT4_8_8_8_UINT = 42,
@@ -125,12 +162,57 @@ enum a4xx_tex_fmt {
        TFMT4_8_UNORM = 4,
        TFMT4_8_8_UNORM = 14,
        TFMT4_8_8_8_8_UNORM = 28,
+       TFMT4_8_8_SNORM = 15,
+       TFMT4_8_8_8_8_SNORM = 29,
+       TFMT4_8_8_UINT = 16,
+       TFMT4_8_8_8_8_UINT = 30,
+       TFMT4_8_8_SINT = 17,
+       TFMT4_8_8_8_8_SINT = 31,
+       TFMT4_16_UINT = 21,
+       TFMT4_16_16_UINT = 41,
+       TFMT4_16_16_16_16_UINT = 54,
+       TFMT4_16_SINT = 22,
+       TFMT4_16_16_SINT = 42,
+       TFMT4_16_16_16_16_SINT = 55,
+       TFMT4_32_UINT = 44,
+       TFMT4_32_32_UINT = 57,
+       TFMT4_32_32_32_32_UINT = 64,
+       TFMT4_32_SINT = 45,
+       TFMT4_32_32_SINT = 58,
+       TFMT4_32_32_32_32_SINT = 65,
        TFMT4_16_FLOAT = 20,
        TFMT4_16_16_FLOAT = 40,
        TFMT4_16_16_16_16_FLOAT = 53,
        TFMT4_32_FLOAT = 43,
        TFMT4_32_32_FLOAT = 56,
        TFMT4_32_32_32_32_FLOAT = 63,
+       TFMT4_9_9_9_E5_FLOAT = 32,
+       TFMT4_11_11_10_FLOAT = 37,
+       TFMT4_ATC_RGB = 100,
+       TFMT4_ATC_RGBA_EXPLICIT = 101,
+       TFMT4_ATC_RGBA_INTERPOLATED = 102,
+       TFMT4_ETC2_RG11_UNORM = 103,
+       TFMT4_ETC2_RG11_SNORM = 104,
+       TFMT4_ETC2_R11_UNORM = 105,
+       TFMT4_ETC2_R11_SNORM = 106,
+       TFMT4_ETC1 = 107,
+       TFMT4_ETC2_RGB8 = 108,
+       TFMT4_ETC2_RGBA8 = 109,
+       TFMT4_ETC2_RGB8A1 = 110,
+       TFMT4_ASTC_4x4 = 111,
+       TFMT4_ASTC_5x4 = 112,
+       TFMT4_ASTC_5x5 = 113,
+       TFMT4_ASTC_6x5 = 114,
+       TFMT4_ASTC_6x6 = 115,
+       TFMT4_ASTC_8x5 = 116,
+       TFMT4_ASTC_8x6 = 117,
+       TFMT4_ASTC_8x8 = 118,
+       TFMT4_ASTC_10x5 = 119,
+       TFMT4_ASTC_10x6 = 120,
+       TFMT4_ASTC_10x8 = 121,
+       TFMT4_ASTC_10x10 = 122,
+       TFMT4_ASTC_12x10 = 123,
+       TFMT4_ASTC_12x12 = 124,
 };
 
 enum a4xx_tex_fetchsize {
@@ -288,13 +370,16 @@ static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
 #define A4XX_RB_RENDER_CONTROL2_YCOORD                         0x00000002
 #define A4XX_RB_RENDER_CONTROL2_ZCOORD                         0x00000004
 #define A4XX_RB_RENDER_CONTROL2_WCOORD                         0x00000008
+#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK                     0x00000010
 #define A4XX_RB_RENDER_CONTROL2_FACENESS                       0x00000020
+#define A4XX_RB_RENDER_CONTROL2_SAMPLEID                       0x00000040
 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK             0x00000380
 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT            7
 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
 {
        return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
 }
+#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR                    0x00000800
 #define A4XX_RB_RENDER_CONTROL2_VARYING                                0x00001000
 
 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
@@ -337,6 +422,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
 {
        return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
 }
+#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB                                0x00002000
 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK             0x007fc000
 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT            14
 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
@@ -464,7 +550,12 @@ static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare
 }
 
 #define REG_A4XX_RB_FS_OUTPUT                                  0x000020f9
-#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND                         0x00000001
+#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK                   0x000000ff
+#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT                  0
+static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
+{
+       return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
+}
 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR                           0x00000100
 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK                    0xffff0000
 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT                   16
@@ -473,12 +564,54 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
        return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
 }
 
-#define REG_A4XX_RB_RENDER_CONTROL3                            0x000020fb
-#define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK         0x0000001f
-#define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT                0
-static inline uint32_t A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(uint32_t val)
+#define REG_A4XX_RB_RENDER_COMPONENTS                          0x000020fb
+#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK                    0x0000000f
+#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT                   0
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK                    0x000000f0
+#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT                   4
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK                    0x00000f00
+#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT                   8
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK                    0x0000f000
+#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT                   12
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK                    0x000f0000
+#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT                   16
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK                    0x00f00000
+#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT                   20
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK                    0x0f000000
+#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT                   24
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
 {
-       return ((val) << A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT) & A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK;
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK                    0xf0000000
+#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT                   28
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
+{
+       return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
 }
 
 #define REG_A4XX_RB_COPY_CONTROL                               0x000020fc
@@ -562,7 +695,12 @@ static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
 }
 
 #define REG_A4XX_RB_FS_OUTPUT_REG                              0x00002100
-#define A4XX_RB_FS_OUTPUT_REG_COLOR_PIPE_ENABLE                        0x00000001
+#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK                                0x0000000f
+#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT                       0
+static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
+{
+       return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
+}
 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z                    0x00000020
 
 #define REG_A4XX_RB_DEPTH_CONTROL                              0x00002101
@@ -1029,6 +1167,9 @@ static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578
 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS                       0x00080000
 
 #define REG_A4XX_SP_INSTR_CACHE_CTRL                           0x000022c1
+#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER                     0x00000080
+#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER                     0x00000100
+#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER                  0x00000400
 
 #define REG_A4XX_SP_VS_CTRL_REG0                               0x000022c4
 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK                  0x00000001
@@ -1248,6 +1389,12 @@ static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
 #define REG_A4XX_SP_FS_LENGTH_REG                              0x000022ef
 
 #define REG_A4XX_SP_FS_OUTPUT_REG                              0x000022f0
+#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK                                0x0000000f
+#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT                       0
+static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
+{
+       return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
+}
 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE                     0x00000080
 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK                        0x0000ff00
 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT               8
@@ -1255,6 +1402,12 @@ static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
 {
        return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
 }
+#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK           0xff000000
+#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT          24
+static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
+{
+       return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
+}
 
 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
 
@@ -1315,6 +1468,12 @@ static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
        return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
 }
 
+#define REG_A4XX_SP_GS_OBJ_START                               0x0000235c
+
+#define REG_A4XX_SP_GS_PVT_MEM_PARAM                           0x0000235d
+
+#define REG_A4XX_SP_GS_PVT_MEM_ADDR                            0x0000235e
+
 #define REG_A4XX_SP_GS_LENGTH_REG                              0x00002360
 
 #define REG_A4XX_VPC_DEBUG_RAM_SEL                             0x00000e60
@@ -1699,6 +1858,14 @@ static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
        return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
 }
 
+#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP                     0x00002076
+#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK                   0xffffffff
+#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT                  0
+static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
+{
+       return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
+}
+
 #define REG_A4XX_GRAS_DEPTH_CONTROL                            0x00002077
 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK                   0x00000003
 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT                  0
@@ -1905,6 +2072,18 @@ static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
 {
        return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
 }
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK           0x0003fc00
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT          10
+static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
+{
+       return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
+}
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK         0x03fc0000
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT                18
+static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
+{
+       return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
+}
 
 #define REG_A4XX_HLSQ_CONTROL_3_REG                            0x000023c3
 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK                    0x000000ff
@@ -2072,6 +2251,18 @@ static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
 #define REG_A4XX_PC_RESTART_INDEX                              0x000021c6
 
 #define REG_A4XX_PC_GS_PARAM                                   0x000021e5
+#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK                    0x000003ff
+#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT                   0
+static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
+{
+       return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
+}
+#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK                                0x01800000
+#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT                       23
+static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
+{
+       return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
+}
 
 #define REG_A4XX_PC_HS_PARAM                                   0x000021e7
 
@@ -2219,6 +2410,7 @@ static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
 
 #define REG_A4XX_TEX_CONST_0                                   0x00000000
 #define A4XX_TEX_CONST_0_TILED                                 0x00000001
+#define A4XX_TEX_CONST_0_SRGB                                  0x00000004
 #define A4XX_TEX_CONST_0_SWIZ_X__MASK                          0x00000070
 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT                         4
 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_blend.c b/src/gallium/drivers/freedreno/a4xx/fd4_blend.c
index b2d494930c46375384b1204d51992197281df27b..396caa532fc77bd5f2e2efe93c8391bf24c41657 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/fd4_blend.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_blend.c
@@ -115,7 +115,7 @@ fd4_blend_state_create(struct pipe_context *pctx,
                                        A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE |
                                        A4XX_RB_MRT_CONTROL_BLEND |
                                        A4XX_RB_MRT_CONTROL_BLEND2;
-                       so->rb_fs_output |= A4XX_RB_FS_OUTPUT_ENABLE_BLEND;
+                       so->rb_fs_output |= A4XX_RB_FS_OUTPUT_ENABLE_BLEND(1);
                }
 
                if (reads_dest)

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index c315a47bb16adc9f0a10046af494470f43fa86a4..bae55dc13eb27770e78aaa41e8765bdba2c75ec9 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -742,8 +742,8 @@ fd4_emit_restore(struct fd_context *ctx)
        OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
        OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
 
-       OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL3, 1);
-       OUT_RING(ring, A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(0xf));
+       OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
+       OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(0xf));
 
        OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
        OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_program.c b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
index 015f6c852251017b7bea065929a51f6d9176268a..7453219ce0010345d9a95d4a1acb35d0e61d89ff 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/fd4_program.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
@@ -392,7 +392,7 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit)
                                        A4XX_RB_RENDER_CONTROL2_YCOORD));
 
        OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
-       OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_COLOR_PIPE_ENABLE |
+       OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(1) |
                        COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
 
        OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);

diff --git a/src/gallium/drivers/freedreno/adreno_common.xml.h b/src/gallium/drivers/freedreno/adreno_common.xml.h
index 163ac548bda36f43577b2cf88176af5777a08c74..174b49513775e94636afb3f82a6d38f605a562e8 100644 (file)
--- a/src/gallium/drivers/freedreno/adreno_common.xml.h
+++ b/src/gallium/drivers/freedreno/adreno_common.xml.h
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14748 bytes, from 2015-04-12 15:01:13)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  57486 bytes, from 2015-04-12 18:10:00)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)

diff --git a/src/gallium/drivers/freedreno/adreno_pm4.xml.h b/src/gallium/drivers/freedreno/adreno_pm4.xml.h
index 05afc66ee8b10389f368c34c50ce7443dc4d20c9..a3d5fffd0e1c5568e37ac459d129bddf558075b6 100644 (file)
--- a/src/gallium/drivers/freedreno/adreno_pm4.xml.h
+++ b/src/gallium/drivers/freedreno/adreno_pm4.xml.h
@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14748 bytes, from 2015-04-12 15:01:13)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  57486 bytes, from 2015-04-12 18:10:00)
 
-Copyright (C) 2013-2014 by the following authors:
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -76,16 +76,10 @@ enum pc_di_primtype {
        DI_PT_LINELOOP = 7,
        DI_PT_RECTLIST = 8,
        DI_PT_POINTLIST_A3XX = 9,
-       DI_PT_QUADLIST = 13,
-       DI_PT_QUADSTRIP = 14,
-       DI_PT_POLYGON = 15,
-       DI_PT_2D_COPY_RECT_LIST_V0 = 16,
-       DI_PT_2D_COPY_RECT_LIST_V1 = 17,
-       DI_PT_2D_COPY_RECT_LIST_V2 = 18,
-       DI_PT_2D_COPY_RECT_LIST_V3 = 19,
-       DI_PT_2D_FILL_RECT_LIST = 20,
-       DI_PT_2D_LINE_STRIP = 21,
-       DI_PT_2D_TRI_STRIP = 22,
+       DI_PT_LINE_ADJ = 10,
+       DI_PT_LINESTRIP_ADJ = 11,
+       DI_PT_TRI_ADJ = 12,
+       DI_PT_TRISTRIP_ADJ = 13,
 };
 
 enum pc_di_src_sel {
@@ -192,6 +186,7 @@ enum adreno_state_block {
        SB_FRAG_TEX = 2,
        SB_FRAG_MIPADDR = 3,
        SB_VERT_SHADER = 4,
+       SB_GEOM_SHADER = 5,
        SB_FRAG_SHADER = 6,
 };