Merge branch 'master' into mwk/xilinx_bufgmap

diff --cc techlibs/xilinx/cells_sim.v
index f1e019d1e1b82b8a572efb5e3d1786f13e28db06,3ad96d7fbbeea60c693a5f24866bcb78b4c39ef4..aeef7f8851ba3707fb0b94cd2af7a3024207b687
--- 1/techlibs/xilinx/cells_sim.v
--- 2/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -340,10 -324,9 +340,10 @@@ module RAM64X1D 
    output DPO, SPO,
    (* abc_scc_break *)
    input  D,
 +  (* clkbuf_sink *)
    input  WCLK,
    (* abc_scc_break *)
-   input WE,
+   input  WE,
    input  A0, A1, A2, A3, A4, A5,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
  );