* interp.c (do_format_3): Get operands correctly and call

        the target function.
        * simops.c: Handle bCC instructions.

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index a026e1fde8cbddfda7eb50ef3bd5243e54b2ca90..969cf6accfcdb7756895a774acbc611a3a5a6b5a 100644 (file)
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,5 +1,9 @@
 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
 
+       * interp.c (do_format_3): Get operands correctly and call
+       the target function.
+       * simops.c: Handle bCC instructions.
+
        * simops.c: Add condition code handling to shift insns.
        Fix minor typos in condition code handling for other insns.
 

diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index bcbb98239d17ad3aaef7462ba91f971c41615949..1cd990e8ecee94f173304c5ba2148295e1b3e740 100644 (file)
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -167,7 +167,12 @@ static void
 do_format_3 (insn)
      uint32 insn;
 {
+  struct hash_entry *h;
   printf("format 3 0x%x\n", insn);
+
+  h = lookup_hash (insn);
+  OP[0] = (((insn & 0x70) >> 4) | ((insn & 0xf800) >> 8)) << 1;
+  (h->ops->func) ();
 }
 
 static void

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index b06c12432913277755ff14e57ff4e02fd8dd9ce8..9eac939f6b05fd7bd893136f4185bc122e261e59 100644 (file)
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -22,99 +22,273 @@ OP_760 ()
 {
 }
 
+/* bv disp9 */
 void
 OP_580 ()
 {
-}
+  unsigned int op0, psw;
+  int temp;
 
-void
-OP_700 ()
-{
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((psw & PSW_OV) != 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bl disp9 */
 void
 OP_581 ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((psw & PSW_CY) != 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* be disp9 */
 void
 OP_582 ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((psw & PSW_Z) != 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bnh disp 9*/
 void
 OP_583 ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bn disp9 */
 void
 OP_584 ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((psw & PSW_S) != 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* br disp9 */
 void
 OP_585 ()
 {
+  unsigned int op0;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  State.pc += op0;
 }
 
+/* blt disp9 */
 void
 OP_586 ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* ble disp9 */
 void
 OP_587 ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((((psw & PSW_Z) != 0)
+       || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bnv disp9 */
 void
 OP_588 ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((psw & PSW_OV) == 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bnl disp9 */
 void
 OP_589 ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((psw & PSW_CY) == 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bne disp9 */
 void
 OP_58A ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((psw & PSW_Z) == 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bh disp9 */
 void
 OP_58B ()
 {
-}
+  unsigned int op0, psw;
+  int temp;
 
-void
-OP_58C ()
-{
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bp disp9 */
 void
-OP_400 ()
+OP_58C ()
 {
-}
+  unsigned int op0, psw;
+  int temp;
 
-void
-OP_160 ()
-{
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((psw & PSW_S) == 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bsa disp9 */
 void
 OP_58D ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((psw & PSW_SAT) != 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bge disp9 */
 void
 OP_58E ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
+/* bgt disp9 */
 void
 OP_58F ()
 {
+  unsigned int op0, psw;
+  int temp;
+
+  temp = (State.regs[OP[0]] << 23) >> 23;
+  op0 = temp;
+  psw = State.psw;
+  
+  if ((((psw & PSW_Z) != 0)
+       || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
+    State.pc += op0;
+  else
+    State.pc += 2;
 }
 
 void
@@ -787,3 +961,18 @@ OP_4007E0 ()
   abort ();
 }
 
+void
+OP_400 ()
+{
+}
+
+void
+OP_160 ()
+{
+}
+
+void
+OP_700 ()
+{
+}
+