radv: store vertex attribute formats as pipeline keys
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 12 Feb 2019 14:09:31 +0000 (15:09 +0100)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Thu, 14 Feb 2019 08:10:09 +0000 (09:10 +0100)
The formats will be used for reducing the number of loaded channels.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/radv_pipeline.c
src/amd/vulkan/radv_private.h
src/amd/vulkan/radv_shader.h

index a9df2b94b936708f58615fd62e43285210399d70..9745a1f2aa7292d5698dfe9f5ec91b7593482f0f 100644 (file)
@@ -1874,13 +1874,27 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
        }
 
        for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
-               unsigned location = input_state->pVertexAttributeDescriptions[i].location;
-               unsigned binding = input_state->pVertexAttributeDescriptions[i].binding;
+               const VkVertexInputAttributeDescription *desc =
+                       &input_state->pVertexAttributeDescriptions[i];
+               const struct vk_format_description *format_desc;
+               unsigned location = desc->location;
+               unsigned binding = desc->binding;
+               unsigned num_format, data_format;
+               int first_non_void;
+
                if (binding_input_rate & (1u << binding)) {
                        key.instance_rate_inputs |= 1u << location;
                        key.instance_rate_divisors[location] = instance_rate_divisors[binding];
                }
 
+               format_desc = vk_format_description(desc->format);
+               first_non_void = vk_format_get_first_non_void_channel(desc->format);
+
+               num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
+               data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
+
+               key.vertex_attribute_formats[location] = data_format | (num_format << 4);
+
                if (pipeline->device->physical_device->rad_info.chip_class <= VI &&
                    pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
                        VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
@@ -1932,8 +1946,10 @@ radv_fill_shader_keys(struct radv_shader_variant_key *keys,
 {
        keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
        keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
-       for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i)
+       for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
                keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
+               keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
+       }
 
        if (nir[MESA_SHADER_TESS_CTRL]) {
                keys[MESA_SHADER_VERTEX].vs.as_ls = true;
index 9ce0724cb9f57c4e87d4800e59ad34aa077be88c..ddabcedc95895d6ffea03da88c0d59b298898bab 100644 (file)
@@ -365,6 +365,7 @@ struct radv_pipeline_cache {
 struct radv_pipeline_key {
        uint32_t instance_rate_inputs;
        uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+       uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
        uint64_t vertex_alpha_adjust;
        unsigned tess_input_vertices;
        uint32_t col_format;
index e0d2737872479811e614a819fb470e41736d1420..0dc965b75f52f18e00f426ea61935365ea133706 100644 (file)
@@ -65,6 +65,7 @@ enum {
 struct radv_vs_variant_key {
        uint32_t instance_rate_inputs;
        uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
+       uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
 
        /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
         * so we may need to fix it up. */