re PR middle-end/20419 (ICE in gen_lowpart_general, at rtlhooks.c:58)

	PR middle-end/20419
	* builtins.c (expand_builtin_signbit): Force the signbit's word
	into an integer register to avoid SUBREGs of floating point modes.

From-SVN: r96328

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0bbe5866c84f3dbaf13a13c216413b8cbb81e049..3e9f384253d276f5285bd0c920afdef3b713e05b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2005-03-11  Roger Sayle  <roger@eyesopen.com>
+
+       PR middle-end/20419
+       * builtins.c (expand_builtin_signbit): Force the signbit's word
+       into an integer register to avoid SUBREGs of floating point modes.
+
 2005-03-12  Kazu Hirata  <kazu@cs.umass.edu>
 
        * cfglayout.c, loop-doloop.c, profile.c, target-def.h,

diff --git a/gcc/builtins.c b/gcc/builtins.c
index 4f464746b9a829c5059f89be013222b03dab8040..e6e07171f742075f677f9f648cdfbeacd46bab73 100644 (file)
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -5003,6 +5003,11 @@ expand_builtin_signbit (tree exp, rtx target)
       bitpos = bitpos % BITS_PER_WORD;
     }
 
+  /* Force the intermediate word_mode (or narrower) result into a
+     register.  This avoids attempting to create paradoxical SUBREGs
+     of floating point modes below.  */
+  temp = force_reg (imode, temp);
+
   /* If the bitpos is within the "result mode" lowpart, the operation
      can be implement with a single bitwise AND.  Otherwise, we need
      a right shift and an AND.  */