split out instructions from openpower/isa/fixedsync.mdwn

diff --git a/openpower/isa/fixedsync.mdwn b/openpower/isa/fixedsync.mdwn
index 5667c07fc4443065e5635e667e75b6c4e064ee47..74c518ca7208d9b469c6908b81c4f43aded345b2 100644 (file)
--- a/openpower/isa/fixedsync.mdwn
+++ b/openpower/isa/fixedsync.mdwn
@@ -2,138 +2,20 @@
 
 <!-- Section 4.6 Fixed-point Synchronisation instructions. Pages 865 - 877 -->
 
-# Instruction Synchronise
+[[!inline pagenames="openpower/isa/fixedsync/isync" raw="yes"]]
 
-XL-Form
+[[!inline pagenames="openpower/isa/fixedsync/lbarx" raw="yes"]]
 
-* isync
+[[!inline pagenames="openpower/isa/fixedsync/lharx" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedsync/lwarx" raw="yes"]]
 
-    # TODO
-    undefined(0)
+[[!inline pagenames="openpower/isa/fixedsync/ldarx" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedsync/stbcx." raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedsync/sthcx." raw="yes"]]
 
-# Load Byte And Reserve Indexed
-
-X-Form
-
-* lbarx RT,RA,RB,EH
-
-Pseudo-code:
-
-    # TODO
-    undefined(0)
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword And Reserve Indexed
-
-X-Form
-
-* lharx RT,RA,RB,EH
-
-Pseudo-code:
-
-    # TODO
-    undefined(0)
-
-Special Registers Altered:
-
-    None
-
-# Load Word And Reserve Indexed
-
-X-Form
-
-* lwarx RT,RA,RB,EH
-
-Pseudo-code:
-
-    # TODO
-    undefined(0)
-
-Special Registers Altered:
-
-    None
-
-# Load Doubleword And Reserve Indexed
-
-X-Form
-
-* ldarx RT,RA,RB,EH
-
-Pseudo-code:
-
-    # TODO
-    undefined(0)
-
-Special Registers Altered:
-
-    None
-
-# Store Byte Conditional Indexed
-
-X-Form
-
-* stbcx. RS,RA,RB
-
-Pseudo-code:
-
-    # TODO
-    undefined(0)
-
-Special Registers Altered:
-
-    CR0
-
-# Store Halfword Conditional Indexed
-
-X-Form
-
-* sthcx. RS,RA,RB
-
-Pseudo-code:
-
-    # TODO
-    undefined(0)
-
-Special Registers Altered:
-
-    CR0
-
-# Store word Conditional Indexed
-
-X-Form
-
-* stwcx. RS,RA,RB
-
-Pseudo-code:
-
-    # TODO
-    undefined(0)
-
-Special Registers Altered:
-
-    CR0
-
-# Store Doubleword Conditional Indexed
-
-X-Form
-
-* stdcx. RS,RA,RB
-
-Pseudo-code:
-
-    # TODO
-    undefined(0)
-
-Special Registers Altered:
-
-    CR0
+[[!inline pagenames="openpower/isa/fixedsync/stwcx." raw="yes"]]
 
+[[!inline pagenames="openpower/isa/fixedsync/stdcx." raw="yes"]]

diff --git a/openpower/isa/fixedsync/isync.mdwn b/openpower/isa/fixedsync/isync.mdwn
new file mode 100644 (file)
index 0000000..9476652
--- /dev/null
+++ b/openpower/isa/fixedsync/isync.mdwn
@@ -0,0 +1,13 @@
+# Instruction Synchronise
+
+XL-Form
+
+* isync
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedsync/isync_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedsync/isync_code.mdwn b/openpower/isa/fixedsync/isync_code.mdwn
new file mode 100644 (file)
index 0000000..a1a7268
--- /dev/null
+++ b/openpower/isa/fixedsync/isync_code.mdwn
@@ -0,0 +1,2 @@
+    # TODO
+    undefined(0)

diff --git a/openpower/isa/fixedsync/lbarx.mdwn b/openpower/isa/fixedsync/lbarx.mdwn
new file mode 100644 (file)
index 0000000..0ace937
--- /dev/null
+++ b/openpower/isa/fixedsync/lbarx.mdwn
@@ -0,0 +1,13 @@
+# Load Byte And Reserve Indexed
+
+X-Form
+
+* lbarx RT,RA,RB,EH
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedsync/lbarx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedsync/lbarx_code.mdwn b/openpower/isa/fixedsync/lbarx_code.mdwn
new file mode 100644 (file)
index 0000000..a1a7268
--- /dev/null
+++ b/openpower/isa/fixedsync/lbarx_code.mdwn
@@ -0,0 +1,2 @@
+    # TODO
+    undefined(0)

diff --git a/openpower/isa/fixedsync/ldarx.mdwn b/openpower/isa/fixedsync/ldarx.mdwn
new file mode 100644 (file)
index 0000000..e423183
--- /dev/null
+++ b/openpower/isa/fixedsync/ldarx.mdwn
@@ -0,0 +1,13 @@
+# Load Doubleword And Reserve Indexed
+
+X-Form
+
+* ldarx RT,RA,RB,EH
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedsync/ldarx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedsync/ldarx_code.mdwn b/openpower/isa/fixedsync/ldarx_code.mdwn
new file mode 100644 (file)
index 0000000..a1a7268
--- /dev/null
+++ b/openpower/isa/fixedsync/ldarx_code.mdwn
@@ -0,0 +1,2 @@
+    # TODO
+    undefined(0)

diff --git a/openpower/isa/fixedsync/lharx.mdwn b/openpower/isa/fixedsync/lharx.mdwn
new file mode 100644 (file)
index 0000000..5d4dfdc
--- /dev/null
+++ b/openpower/isa/fixedsync/lharx.mdwn
@@ -0,0 +1,13 @@
+# Load Halfword And Reserve Indexed
+
+X-Form
+
+* lharx RT,RA,RB,EH
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedsync/lharx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedsync/lharx_code.mdwn b/openpower/isa/fixedsync/lharx_code.mdwn
new file mode 100644 (file)
index 0000000..a1a7268
--- /dev/null
+++ b/openpower/isa/fixedsync/lharx_code.mdwn
@@ -0,0 +1,2 @@
+    # TODO
+    undefined(0)

diff --git a/openpower/isa/fixedsync/lwarx.mdwn b/openpower/isa/fixedsync/lwarx.mdwn
new file mode 100644 (file)
index 0000000..766a8cc
--- /dev/null
+++ b/openpower/isa/fixedsync/lwarx.mdwn
@@ -0,0 +1,13 @@
+# Load Word And Reserve Indexed
+
+X-Form
+
+* lwarx RT,RA,RB,EH
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedsync/lwarx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedsync/lwarx_code.mdwn b/openpower/isa/fixedsync/lwarx_code.mdwn
new file mode 100644 (file)
index 0000000..a1a7268
--- /dev/null
+++ b/openpower/isa/fixedsync/lwarx_code.mdwn
@@ -0,0 +1,2 @@
+    # TODO
+    undefined(0)

diff --git a/openpower/isa/fixedsync/stbcx..mdwn b/openpower/isa/fixedsync/stbcx..mdwn
new file mode 100644 (file)
index 0000000..8ac7820
--- /dev/null
+++ b/openpower/isa/fixedsync/stbcx..mdwn
@@ -0,0 +1,13 @@
+# Store Byte Conditional Indexed
+
+X-Form
+
+* stbcx. RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedsync/stbcx._code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0

diff --git a/openpower/isa/fixedsync/stbcx._code.mdwn b/openpower/isa/fixedsync/stbcx._code.mdwn
new file mode 100644 (file)
index 0000000..a1a7268
--- /dev/null
+++ b/openpower/isa/fixedsync/stbcx._code.mdwn
@@ -0,0 +1,2 @@
+    # TODO
+    undefined(0)

diff --git a/openpower/isa/fixedsync/stdcx..mdwn b/openpower/isa/fixedsync/stdcx..mdwn
new file mode 100644 (file)
index 0000000..f66f59e
--- /dev/null
+++ b/openpower/isa/fixedsync/stdcx..mdwn
@@ -0,0 +1,14 @@
+# Store Doubleword Conditional Indexed
+
+X-Form
+
+* stdcx. RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedsync/stdcx._code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0
+

diff --git a/openpower/isa/fixedsync/stdcx._code.mdwn b/openpower/isa/fixedsync/stdcx._code.mdwn
new file mode 100644 (file)
index 0000000..a1a7268
--- /dev/null
+++ b/openpower/isa/fixedsync/stdcx._code.mdwn
@@ -0,0 +1,2 @@
+    # TODO
+    undefined(0)

diff --git a/openpower/isa/fixedsync/sthcx..mdwn b/openpower/isa/fixedsync/sthcx..mdwn
new file mode 100644 (file)
index 0000000..d687349
--- /dev/null
+++ b/openpower/isa/fixedsync/sthcx..mdwn
@@ -0,0 +1,13 @@
+# Store Halfword Conditional Indexed
+
+X-Form
+
+* sthcx. RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedsync/sthcx._code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0

diff --git a/openpower/isa/fixedsync/sthcx._code.mdwn b/openpower/isa/fixedsync/sthcx._code.mdwn
new file mode 100644 (file)
index 0000000..a1a7268
--- /dev/null
+++ b/openpower/isa/fixedsync/sthcx._code.mdwn
@@ -0,0 +1,2 @@
+    # TODO
+    undefined(0)

diff --git a/openpower/isa/fixedsync/stwcx..mdwn b/openpower/isa/fixedsync/stwcx..mdwn
new file mode 100644 (file)
index 0000000..469ba5e
--- /dev/null
+++ b/openpower/isa/fixedsync/stwcx..mdwn
@@ -0,0 +1,13 @@
+# Store word Conditional Indexed
+
+X-Form
+
+* stwcx. RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedsync/stwcx._code" raw="yes"]]
+
+Special Registers Altered:
+
+    CR0

diff --git a/openpower/isa/fixedsync/stwcx._code.mdwn b/openpower/isa/fixedsync/stwcx._code.mdwn
new file mode 100644 (file)
index 0000000..a1a7268
--- /dev/null
+++ b/openpower/isa/fixedsync/stwcx._code.mdwn
@@ -0,0 +1,2 @@
+    # TODO
+    undefined(0)