Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
and individual unit tests for the
[Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
-* [Litex sim.py](https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;hb=HEAD)
+* simulation
with some peripherals developed in c++ as verilator modules
* nmigen-based OpenPOWER Libre-SOC core co-simulation such as
this unit test,