Merge remote-tracking branch 'origin/master' into typed_pad_ctrl

diff --combined src/main/scala/devices/uart/UARTPeriphery.scala
index d42850f88eca4388a571ac86e47743c69406beef,677394f2581ca436bbf565af0d4f568cff208c23..5564fef60fd934473aabb779331411cb68188917
--- 1/src/main/scala/devices/uart/UARTPeriphery.scala
--- 2/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@@ -2,19 -2,19 +2,20 @@@
  package sifive.blocks.devices.uart
  
  import Chisel._
 +import chisel3.experimental.{withClockAndReset}
  import freechips.rocketchip.config.Field
- import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+ import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
  import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 -import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
 +import sifive.blocks.devices.pinctrl.{Pin}
  import sifive.blocks.util.ShiftRegisterInit
  
  case object PeripheryUARTKey extends Field[Seq[UARTParams]]
  
  trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
-   val uartParams = p(PeripheryUARTKey)  
+   val uartParams = p(PeripheryUARTKey)
+   val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
    val uarts = uartParams map { params =>
-     val uart = LazyModule(new TLUART(pbus.beatBytes, params))
+     val uart = LazyModule(new TLUART(pbus.beatBytes, params.copy(divisorInit = divinit)))
      uart.node := pbus.toVariableWidthSlaves
      ibus.fromSync := uart.intnode
      uart
@@@ -22,36 -22,40 +23,36 @@@
  }
  
  trait HasPeripheryUARTBundle {
 -  val uarts: Vec[UARTPortIO]
 +  val uart: Vec[UARTPortIO]
  
    def tieoffUARTs(dummy: Int = 1) {
 -    uarts.foreach { _.rxd := UInt(1) }
 +    uart.foreach { _.rxd := UInt(1) }
    }
  
 -  def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
 -    val pins = Module(new UARTGPIOPort(syncStages))
 -    pins.io.uart <> u
 -    pins.io.pins
 -  }
  }
  
  trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
    val outer: HasPeripheryUART
 -  val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
 +  val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
  
 -  (uarts zip outer.uarts).foreach { case (io, device) =>
 +  (uart zip outer.uarts).foreach { case (io, device) =>
      io <> device.module.io.port
    }
  }
  
 -class UARTPinsIO extends Bundle {
 -  val rxd = new GPIOPin
 -  val txd = new GPIOPin
 -}
 +class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
 +  val rxd = pingen()
 +  val txd = pingen()
  
 -class UARTGPIOPort(syncStages: Int = 0) extends Module {
 -  val io = new Bundle{
 -    val uart = new UARTPortIO().flip()
 -    val pins = new UARTPinsIO
 -  }
 +  override def cloneType: this.type =
 +    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
  
 -  GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
 -  val rxd = GPIOInputPinCtrl(io.pins.rxd)
 -  io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
 +  def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
 +    withClockAndReset(clock, reset) {
 +      txd.outputPin(uart.txd)
 +      val rxd_t = rxd.inputPin()
 +      uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
 +    }
 +  }
  }
 +