ev5.md: Don't combine shift and mvi insns in one reservation.

        * config/alpha/ev5.md: Don't combine shift and mvi insns in one
        reservation.

From-SVN: r54453

diff --git a/gcc/config/alpha/ev5.md b/gcc/config/alpha/ev5.md
index f0dfbdf22e6fa1dcc4a4944388e91f9206407c8f..69aa4a817aa3f180b6f8ba524a16af4f65dc1eb7 100644 (file)
--- a/gcc/config/alpha/ev5.md
+++ b/gcc/config/alpha/ev5.md
@@ -64,9 +64,14 @@
        (eq_attr "type" "jsr"))
   "ev5_e1")
 
-(define_insn_reservation "ev5_shiftmvi" 2
+(define_insn_reservation "ev5_shift" 1
   (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "shift,mvi"))
+       (eq_attr "type" "shift"))
+  "ev5_e0")
+
+(define_insn_reservation "ev5_mvi" 2
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "mvi"))
   "ev5_e0")
 
 (define_insn_reservation "ev5_cmov" 2
@@ -119,7 +124,7 @@
 ; Model this instead with increased latency on the input instruction.
 
 (define_bypass 3
-  "ev5_ld,ev5_shiftmvi,ev5_cmov,ev5_iadd,ev5_ilogcmp"
+  "ev5_ld,ev5_shift,ev5_mvi,ev5_cmov,ev5_iadd,ev5_ilogcmp"
   "ev5_imull,ev5_imulq,ev5_imulh")
 
 (define_bypass  9 "ev5_imull" "ev5_imull,ev5_imulq,ev5_imulh")