Bugfix in simlib.v for iverilog

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 76aa4a52d0f133f06741ac12e884e5a51e173c21..c2f6cb278cd7a831cb983d6136a4bf06feea95fb 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -455,11 +455,12 @@ input [B_WIDTH-1:0] B;
 output [Y_WIDTH-1:0] Y;
 
 generate
-       if (B_SIGNED) begin:BLOCK1
-               assign Y = A[$signed(B) +: Y_WIDTH];
-       end else begin:BLOCK2
-               assign Y = A[B +: Y_WIDTH];
-       end
+       if (Y_WIDTH > 0)
+               if (B_SIGNED) begin:BLOCK1
+                       assign Y = A[$signed(B) +: Y_WIDTH];
+               end else begin:BLOCK2
+                       assign Y = A[B +: Y_WIDTH];
+               end
 endgenerate
 
 endmodule