[AArch64] Merge SVE FMAXNM/FMINNM patterns

This patch makes us use the same define_insn for both the smax/smin
and fmax/fmin optabs.  It also continues the process started by
the earlier FP unary patch of moving predicated FP patterns from
rtx codes to unspecs.

There's no need to handle the FMAX and FMIN instructions until
the ACLE patch, since we only use FMAXNM and FMINNM at present.

2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (SVE_COND_FP_MAXMIN_PUBLIC): New
	int iterator.
	(maxmin_uns_op): Handle UNSPEC_COND_FMAXNM and UNSPEC_COND_FMINNM.
	* config/aarch64/aarch64-sve.md
	(<FMAXMIN:su><FMAXMIN:maxmin><SVE_F:mode>3): Rename to...
	(<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3): ...this and
	use a single unspec for the rhs.
	(*<su><maxmin><mode>3): Delete.
	(<maxmin_uns><SVE_F:mode>3): Use a single unspec for the rhs.

From-SVN: r274188

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3e31681f7378cfe38c2a3ef18fe8c807594952bb..91b314b11d232d32888531e345092c54b8fdb805 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/iterators.md (SVE_COND_FP_MAXMIN_PUBLIC): New
+       int iterator.
+       (maxmin_uns_op): Handle UNSPEC_COND_FMAXNM and UNSPEC_COND_FMINNM.
+       * config/aarch64/aarch64-sve.md
+       (<FMAXMIN:su><FMAXMIN:maxmin><SVE_F:mode>3): Rename to...
+       (<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3): ...this and
+       use a single unspec for the rhs.
+       (*<su><maxmin><mode>3): Delete.
+       (<maxmin_uns><SVE_F:mode>3): Use a single unspec for the rhs.
+
 2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
 
        * config/aarch64/iterators.md (UNSPEC_COND_FABS, UNSPEC_COND_FNEG)

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 1f5153a0e443d5a01745405c58a1897558038cfa..a9943295d188c764e60b4c5e612213fedfee2026 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -2186,69 +2186,51 @@
 ;; ---- [FP] Maximum and minimum
 ;; -------------------------------------------------------------------------
 ;; Includes:
-;; - FMAX
 ;; - FMAXNM
-;; - FMIN
 ;; - FMINNM
 ;; -------------------------------------------------------------------------
 
-;; Unpredicated floating-point MAX/MIN.
-(define_expand "<su><maxmin><mode>3"
+;; Unpredicated floating-point MAX/MIN (the rtx codes).  These are more
+;; relaxed than fmax/fmin, but we implement them in the same way.
+(define_expand "<optab><mode>3"
   [(set (match_operand:SVE_F 0 "register_operand")
        (unspec:SVE_F
          [(match_dup 3)
-          (FMAXMIN:SVE_F (match_operand:SVE_F 1 "register_operand")
-                         (match_operand:SVE_F 2 "register_operand"))]
-         UNSPEC_MERGE_PTRUE))]
+          (match_operand:SVE_F 1 "register_operand")
+          (match_operand:SVE_F 2 "register_operand")]
+         SVE_COND_FP_MAXMIN_PUBLIC))]
   "TARGET_SVE"
   {
     operands[3] = aarch64_ptrue_reg (<VPRED>mode);
   }
 )
 
-;; Floating-point MAX/MIN predicated with a PTRUE.
-(define_insn "*<su><maxmin><mode>3"
-  [(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w")
-       (unspec:SVE_F
-         [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
-          (FMAXMIN:SVE_F (match_operand:SVE_F 2 "register_operand" "%0, w")
-                         (match_operand:SVE_F 3 "register_operand" "w, w"))]
-         UNSPEC_MERGE_PTRUE))]
-  "TARGET_SVE"
-  "@
-   f<maxmin>nm\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
-   movprfx\t%0, %2\;f<maxmin>nm\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
-  [(set_attr "movprfx" "*,yes")]
-)
-
-;; Unpredicated fmax/fmin.
+;; Unpredicated fmax/fmin (the libm functions).
 (define_expand "<maxmin_uns><mode>3"
   [(set (match_operand:SVE_F 0 "register_operand")
        (unspec:SVE_F
          [(match_dup 3)
-          (unspec:SVE_F [(match_operand:SVE_F 1 "register_operand")
-                         (match_operand:SVE_F 2 "register_operand")]
-                        FMAXMIN_UNS)]
-         UNSPEC_MERGE_PTRUE))]
+          (match_operand:SVE_F 1 "register_operand")
+          (match_operand:SVE_F 2 "register_operand")]
+         SVE_COND_FP_MAXMIN_PUBLIC))]
   "TARGET_SVE"
   {
     operands[3] = aarch64_ptrue_reg (<VPRED>mode);
   }
 )
 
-;; fmax/fmin predicated with a PTRUE.
-(define_insn "*<maxmin_uns><mode>3"
+;; Predicated floating-point maximum/minimum.
+(define_insn "*<optab><mode>3"
   [(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w")
        (unspec:SVE_F
          [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
-          (unspec:SVE_F [(match_operand:SVE_F 2 "register_operand" "%0, w")
-                         (match_operand:SVE_F 3 "register_operand" "w, w")]
-                        FMAXMIN_UNS)]
-         UNSPEC_MERGE_PTRUE))]
+          (match_operand:SVE_F 2 "register_operand" "%0, w")
+          (match_operand:SVE_F 3 "register_operand" "w, w")]
+         SVE_COND_FP_MAXMIN_PUBLIC))]
   "TARGET_SVE"
   "@
-   <maxmin_uns_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
-   movprfx\t%0, %2\;<maxmin_uns_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
+   <sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
+   movprfx\t%0, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
   [(set_attr "movprfx" "*,yes")]
 )
 

diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 1e39266cee82e77012fb791766faa0ab49219d3a..a6e2b1e6d276ae749dcb1db8bbc9e0673fd577d1 100644 (file)
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -1630,6 +1630,11 @@
                                         UNSPEC_COND_FMUL
                                         UNSPEC_COND_FSUB])
 
+;; Floating-point max/min operations that correspond to optabs,
+;; as opposed to those that are internal to the port.
+(define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM
+                                               UNSPEC_COND_FMINNM])
+
 (define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
                                          UNSPEC_COND_FMLS
                                          UNSPEC_COND_FNMLA
@@ -1709,7 +1714,9 @@
                              (UNSPEC_FMINNMV "smin")
                              (UNSPEC_FMINV "smin_nan")
                              (UNSPEC_FMAXNM "fmax")
-                             (UNSPEC_FMINNM "fmin")])
+                             (UNSPEC_FMINNM "fmin")
+                             (UNSPEC_COND_FMAXNM "fmax")
+                             (UNSPEC_COND_FMINNM "fmin")])
 
 (define_int_attr  maxmin_uns_op [(UNSPEC_UMAXV "umax")
                                 (UNSPEC_UMINV "umin")