radeonsi: force NaNs to 0

This fixes incorrect rendering in Unreal Engine demos.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83510

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 3a5b0ae5fee4098a0dde6cbff630bf157e748951..355f8aaf454b986eedfcf940b3fdb513aa789125 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -64,7 +64,8 @@ static void si_shader_es(struct si_shader *shader)
        si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
                       S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
                       S_00B328_SGPRS((num_sgprs - 1) / 8) |
-                      S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
+                      S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
+                      S_00B328_DX10_CLAMP(1));
        si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
                       S_00B32C_USER_SGPR(num_user_sgprs));
 }
@@ -132,7 +133,8 @@ static void si_shader_gs(struct si_shader *shader)
 
        si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
                       S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
-                      S_00B228_SGPRS((num_sgprs - 1) / 8));
+                      S_00B228_SGPRS((num_sgprs - 1) / 8) |
+                      S_00B228_DX10_CLAMP(1));
        si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
                       S_00B22C_USER_SGPR(num_user_sgprs));
 }
@@ -206,7 +208,8 @@ static void si_shader_vs(struct si_shader *shader)
        si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
                       S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
                       S_00B128_SGPRS((num_sgprs - 1) / 8) |
-                      S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
+                      S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
+                      S_00B128_DX10_CLAMP(1));
        si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
                       S_00B12C_USER_SGPR(num_user_sgprs) |
                       S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
@@ -304,7 +307,8 @@ static void si_shader_ps(struct si_shader *shader)
 
        si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
                       S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
-                      S_00B028_SGPRS((num_sgprs - 1) / 8));
+                      S_00B028_SGPRS((num_sgprs - 1) / 8) |
+                      S_00B028_DX10_CLAMP(1));
        si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
                       S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
                       S_00B02C_USER_SGPR(num_user_sgprs));